Arria V Device Overview

ID 683440
Date 11/20/2020
Public
Document Table of Contents

1.8. Clock Networks and PLL Clock Sources

650 MHz Arria® V devices have 16 global clock networks capable of up to operation. The clock network architecture is based on Intel® 's global, quadrant, and peripheral clock structure. This clock structure is supported by dedicated clock input pins and fractional PLLs.

Note: To reduce power consumption, the Intel® Quartus® Prime software identifies all unused sections of the clock network and powers them down.

PLL Features

The PLLs in the Arria® V devices support the following features:

  • Frequency synthesis
  • On-chip clock deskew
  • Jitter attenuation
  • Counter reconfiguration
  • Programmable output clock duty cycles
  • PLL cascading
  • Reference clock switchover
  • Programmable bandwidth
  • Dynamic phase shift
  • Zero delay buffers

Fractional PLL

In addition to integer PLLs, the Arria® V devices use a fractional PLL architecture. The devices have up to 16 PLLs, each with 18 output counters. One fractional PLL can use up to 18 output counters and two adjacent fractional PLLs share the 18 output counters. You can use the output counters to reduce PLL usage in two ways:

  • Reduce the number of oscillators that are required on your board by using fractional PLLs
  • Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies from a single reference clock source

If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency synthesis—removing the need for off-chip reference clock sources in your design.

The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose fractional PLLs by the FPGA fabric.

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