Arria V Device Overview

ID 683440
Date 11/20/2020
Public
Document Table of Contents

1.3.2.2. Maximum Resources

Table 6.  Maximum Resource Counts for Arria V GT Devices
Resource Member Code
C3 C7 D3 D7
Logic Elements (LE) (K) 156 242 362 504
ALM 58,900 91,680 136,880 190,240
Register 235,600 366,720 547,520 760,960
Memory (Kb) M10K 10,510 13,660 17,260 24,140
MLAB 961 1,448 2,098 2,906
Variable-precision DSP Block 396 800 1,045 1,156
18 x 18 Multiplier 792 1,600 2,090 2,312
PLL 10 12 12 16
Transceiver 6 Gbps 4 3 (9) 6 (24) 6 (24) 6 (36)
10 Gbps 5 4 12 12 20
GPIO6 416 544 704 704
LVDS Transmitter 68 120 160 160
Receiver 80 136 176 176
PCIe Hard IP Block 1 2 2 2
Hard Memory Controller 2 4 4 4
4 The 6 Gbps transceiver counts are for dedicated 6-Gbps channels. You can also configure any pair of 10 Gbps channels as three 6 Gbps channels-the total number of 6 Gbps channels are shown in brackets.
5 Chip-to-chip connections only. For 10 Gbps channel usage conditions, refer to the Transceiver Architecture in Arria V Devices chapter.
6 The number of GPIOs does not include transceiver I/Os. In the Intel® Quartus® Prime software, the number of user I/Os includes transceiver I/Os.

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