1.1. Key Advantages of Arria® V Devices
1.2. Summary of Arria® V Features
1.3. Arria® V Device Variants and Packages
1.4. I/O Vertical Migration for Arria® V Devices
1.5. Adaptive Logic Module
1.6. Variable-Precision DSP Block
1.7. Embedded Memory Blocks
1.8. Clock Networks and PLL Clock Sources
1.9. FPGA General Purpose I/O
1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP
1.11. External Memory Interface
1.12. Low-Power Serial Transceivers
1.13. SoC with HPS
1.14. Dynamic Reconfiguration
1.15. Enhanced Configuration and Configuration via Protocol
1.16. Power Management
1.17. Document Revision History
1.11.1. Hard and Soft Memory Controllers
Arria® V GX,GT, SX, and ST devices support up to four hard memory controllers for DDR3 and DDR2 SDRAM devices. Each controller supports 8 to 32 bit components of up to 4 gigabits (Gb) in density with two chip selects and optional ECC. For the Arria® V SoC devices, an additional hard memory controller in the HPS supports DDR3, DDR2, and LPDDR2 SDRAM devices.
All Arria® V devices support soft memory controllers for DDR3, DDR2, and LPDDR2 SDRAM devices, QDR II+, QDR II, and DDR II+ SRAM devices, and RLDRAM II devices for maximum flexibility.
Note: DDR3 SDRAM leveling is supported only in Arria® V GZ devices.