Arria V Device Overview

ID 683440
Date 11/20/2020
Public
Document Table of Contents

1.17. Document Revision History

Document Version Changes
2020.11.20 Removed information about partial reconfiguration.
2020.06.15
  • Removed the "ES" from the list of optional suffix from the following figures:
    • Sample Ordering Code and Available Options for Arria V GX Devices
    • Sample Ordering Code and Available Options for Arria V GT Devices
    • Sample Ordering Code and Available Options for Arria V SX Devices
    • Sample Ordering Code and Available Options for Arria V ST Devices
  • Updated the RoHS information to include the "P" suffix in the sample ordering code for all the Arria V devices.
2019.04.16 Updated RoHS and optional suffix information in sample ordering code and available options diagrams for all the Arria V devices.
Date Version Changes
December 2015 2015.12.21
  • Updated RoHS and optional suffix information in sample ordering code and available options diagrams for Arria V GX and GT devices.
  • Changed instances of Quartus II to Quartus Prime.
January 2015 2015.01.23
  • Updated package dimension for Arria® V GZ H780 package from 29 mm to 33 mm.
  • Updated dual-core ARM Cortex-A9 MPCore processor maximum frequency from 800 MHz to 1.05 GHz.
December 2013 2013.12.26
  • 10-Gbps Ethernet (10GbE) PCS and Interlaken PCS are for Arria V GZ only.
  • Removed "Preliminary" texts from Ordering Code figures, Maximum Resources, Package Plan and I/O Vertical Migration tables.
  • Added link to Altera Product Selector for each device variant.
  • Added leaded package options.
  • Removed the note "The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs." for all PLLs in the Maximum Resource Counts table.
  • Corrected FPGA GPIO for Arria® V SX B3 and B5 as well as Arria® V ST D3 and D5 F896 package from 170 to 250.
  • Corrected FPGA GPIO for Arria® V SX B3 and B5 as well as Arria® V ST D3 and D5 F1152 package from 350 to 385.
  • Corrected FPGA GPIO for Arria® V SX B3 and B5 as well as Arria® V ST D3 and D5 F1517 package from 528 to 540.
  • Corrected LVDS Transmitter for Arria® V SX B3 and B5 as well as Arria® V ST D3 and D5 devices from 121 to 120.
  • Added links to Altera's External Memory Spec Estimator tool to the topics listing the external memory interface performance.
  • Added x2 for PCIe Gen3, Gen 2, and Gen 1.
August 2013 2013.08.19
  • Removed the note about the PCIe hard IP on the right side of the device in the F896 package of the Arria® V GX variant. These devices do not have PCIe hard IP on the right side.
  • Added transceiver speed grade 6 to the available options of the Arria® V SX variant.
  • Corrected the maximum LVDS transmitter channel counts for the Arria® V GX A1 and A3 devices from 68 to 67.
  • Corrected the maximum FPGA GPIO count for Arria® V ST D5 devices from 540 to 528.
June 2013 2013.06.03
May 2013 2013.05.06
  • Moved all links to the Related Information section of respective topics for easy reference.
  • Added link to the known document issues in the Knowledge Base.
  • Updated the available options, maximum resource counts, and per package information for the Arria® V SX and ST device variants.
  • Updated the variable DSP multipliers counts for the Arria® V SX and ST device variants.
  • Clarified that partial reconfiguration is an advanced feature. Contact Altera for support of the feature.
  • Added footnote to clarify that MLAB 64 bits depth is available only for Arria V GZ devices.
  • Updated description about power-up sequence requirement for device migration to improve clarity.
January 2013 2013.01.11
  • Added the L optional suffix to the Arria V GZ ordering code for the –I3 speed grade.
  • Added a note about the power-up sequence requirement if you plan to migrate your design from the Arria® V GX A5 and A7, and Arria® V GT C7 devices to other Arria® V devices.
November 2012 2012.11.19
  • Updated the summary of features.
  • Updated Arria V GZ information regarding 3.3 V I/O support.
  • Removed Arria V GZ engineering sample ordering code.
  • Updated the maximum resource counts for Arria V GX and GZ.
  • Updated Arria V ST ordering codes for transceiver count.
  • Updated transceiver counts for Arria V ST packages.
  • Added simplified floorplan diagrams for Arria V GZ, SX, and ST.
  • Added FPP x32 configuration mode for Arria V GZ only.
  • Updated CvP (PCIe) remote system update support information.
  • Added HPS external memory performance information.
  • Updated template.
October 2012 3.0
  • Added Arria V GZ information.
  • Updated Table 1, Table 2, Table 3, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, and Table 21.
  • Added the “Arria V GZ” section.
  • Added Table 8, Table 9 and Table 22.
July 2012 2.1
  • Added –I3 speed grade to Figure 1 for Arria V GX devices.
  • Updated the 6-Gbps transceiver speed from 6.553 Gbps to 6.5536 Gbps in Figure 3 and Figure 1.
June 2012 2.0
  • Restructured the document.
  • Added the “Embedded Memory Capacity” and “Embedded Memory Configurations” sections.
  • Added Table 1, Table 3, Table 12, Table 15, and Table 16.
  • Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9, Table 10, Table 11, Table 13, Table 14, and Table 19.
  • Updated Figure 1, Figure 2, Figure 3, Figure 4, and Figure 8.
  • Updated the “FPGA Configuration and Processor Booting” and “Hardware and Software Development” sections.
  • Text edits throughout the document.
February 2012 1.3
  • Updated Table 1–7 and Table 1–8.
  • Updated Figure 1–9 and Figure 1–10.
  • Minor text edits.
December 2011 1.2

Minor text edits.

November 2011 1.1
  • Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–6, Table 1–7, Table 1–9, and Table 1–10.
  • Added “SoC FPGA with HPS” section.
  • Updated “Clock Networks and PLL Clock Sources” and “Ordering Information” sections.
  • Updated Figure 1–5.
  • Added Figure 1–6.
  • Minor text edits.
August 2011 1.0 Initial release.

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