Arria V Device Overview

ID 683440
Date 11/20/2020
Public
Document Table of Contents

1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP

Arria® V devices contain PCIe* hard IP that is designed for performance and ease-of-use. The PCIe* hard IP consists of the MAC, data link, and transaction layers.

The PCIe* hard IP supports PCIe* Gen3, Gen 2, and Gen 1 end point and root port for up to x8 lane configuration.

The PCIe* endpoint support includes multifunction support for up to eight functions, as shown in the following figure. The integrated multifunction support reduces the FPGA logic requirements by up to 20,000 LEs for PCIe* designs that require multiple peripherals.

Figure 8.  PCIe* Multifunction for Arria® V Devices


The Arria® V PCIe* hard IP operates independently from the core logic. This independent operation allows the PCIe* link to wake up and complete link training in less than 100 ms while the Arria® V device completes loading the programming file for the rest of the device.

In addition, the PCIe* hard IP in the Arria® V device provides improved end-to-end datapath protection using ECC.

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