Arria V Device Overview

ID 683440
Date 11/20/2020
Public
Document Table of Contents

1.1. Key Advantages of Arria® V Devices

Table 1.   Key Advantages of the Arria® V Device Family

Advantage

Supporting Feature

Lowest static power in its class
  • Built on TSMC's 28 nm process technology and includes an abundance of hard intellectual property (IP) blocks
  • Power-optimized MultiTrack routing and core architecture
  • Up to 50% lower power consumption than the previous generation device
  • Lowest power transceivers of any midrange family
Improved logic integration and differentiation capabilities
  • 8-input adaptive logic module (ALM)
  • Up to 38.38 megabits (Mb) of embedded memory
  • Variable-precision digital signal processing (DSP) blocks
Increased bandwidth capacity
  • Serial data rates up to 12.5 Gbps
  • Hard memory controllers
Hard processor system (HPS) with integrated ARM® Cortex™-A9 MPCore processor
  • Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard IP, and an FPGA in a single Arria® V system-on-a-chip (SoC)
  • Supports over 128 Gbps peak bandwidth with integrated data coherency between the processor and the FPGA fabric
Lowest system cost
  • Requires as few as four power supplies to operate
  • Available in thermal composite flip chip ball-grid array (BGA) packaging
  • Includes innovative features such as Configuration via Protocol (CvP) and design security

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