Arria® V Device Overview

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ID 683440
Date 11/20/2020
Public
Document Table of Contents
Document Table of Contents x
1. Arria V Device Overview
1. Arria V Device Overview x
1.1. Key Advantages of Arria® V Devices 1.2. Summary of Arria® V Features 1.3. Arria® V Device Variants and Packages 1.4. I/O Vertical Migration for Arria® V Devices 1.5. Adaptive Logic Module 1.6. Variable-Precision DSP Block 1.7. Embedded Memory Blocks 1.8. Clock Networks and PLL Clock Sources 1.9. FPGA General Purpose I/O 1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP 1.11. External Memory Interface 1.12. Low-Power Serial Transceivers 1.13. SoC with HPS 1.14. Dynamic Reconfiguration 1.15. Enhanced Configuration and Configuration via Protocol 1.16. Power Management 1.17. Document Revision History
1.3. Arria® V Device Variants and Packages x
1.3.1. Arria V GX 1.3.2. Arria V GT 1.3.3. Arria V GZ 1.3.4. Arria V SX 1.3.5. Arria V ST
1.3.1. Arria V GX x
1.3.1.1. Available Options 1.3.1.2. Maximum Resources 1.3.1.3. Package Plan
1.3.2. Arria V GT x
1.3.2.1. Available Options 1.3.2.2. Maximum Resources 1.3.2.3. Package Plan
1.3.3. Arria V GZ x
1.3.3.1. Available Options 1.3.3.2. Maximum Resources 1.3.3.3. Package Plan
1.3.4. Arria V SX x
1.3.4.1. Available Options 1.3.4.2. Maximum Resources 1.3.4.3. Package Plan
1.3.5. Arria V ST x
1.3.5.1. Available Options 1.3.5.2. Maximum Resources 1.3.5.3. Package Plan
1.7. Embedded Memory Blocks x
1.7.1. Types of Embedded Memory 1.7.2. Embedded Memory Capacity in Arria V Devices 1.7.3. Embedded Memory Configurations
1.11. External Memory Interface x
1.11.1. Hard and Soft Memory Controllers 1.11.2. External Memory Performance 1.11.3. HPS External Memory Performance
1.12. Low-Power Serial Transceivers x
1.12.1. Transceiver Channels 1.12.2. PMA Features 1.12.3. PCS Features
1.13. SoC with HPS x
1.13.1. HPS Features 1.13.2. FPGA Configuration and Processor Booting 1.13.3. Hardware and Software Development
1.13.1. HPS Features x
1.13.1.1. System Peripherals and Debug Access Port 1.13.1.2. HPS–FPGA AXI Bridges 1.13.1.3. HPS SDRAM Controller Subsystem
1.14. Dynamic Reconfiguration x
1.14.1. Dynamic Reconfiguration
1. Arria V Device Overview

1.7.2. Embedded Memory Capacity in Arria V Devices

Table 16.  Embedded Memory Capacity and Distribution in Arria V Devices
Variant Member Code M20K M10K MLAB Total RAM Bit (Kb)
Block RAM Bit (Kb) Block RAM Bit (Kb) Block RAM Bit (Kb)
Arria V GX A1 — — 800 8,000 741 463 8,463
A3 — — 1,051 10,510 1538 961 11,471
A5 — — 1,180 11,800 1877 1,173 12,973
A7 — — 1,366 13,660 2317 1,448 15,108
B1 — — 1,510 15,100 2964 1,852 16,952
B3 — — 1,726 17,260 3357 2,098 19,358
B5 — — 2,054 20,540 4052 2,532 23,072
B7 — — 2,414 24,140 4650 2,906 27,046
Arria V GT C3 — — 1,051 10,510 1538 961 11,471
C7 — — 1,366 13,660 2317 1,448 15,108
D3 — — 1,726 17,260 3357 2,098 19,358
D7 — — 2,414 24,140 4650 2,906 27,046
Arria V GZ E1 585 11,700 — — 4,151 2,594 14,294
E3 957 19,140 — — 6,792 4,245 23,385
E5 1,440 28,800 — — 7,548 4,718 33,518
E7 1,700 34,000 — — 8,490 5,306 39,306
Arria V SX B3 — — 1,729 17,290 3223 2,014 19,304
B5 — — 2,282 22,820 4253 2,658 25,478
Arria V ST D3 — — 1,729 17,290 3223 2,014 19,304
D5 — — 2,282 22,820 4253 2,658 25,478
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