Arria V Device Overview

ID 683440
Date 11/20/2020
Public
Document Table of Contents

1.4. I/O Vertical Migration for Arria® V Devices

Figure 6. Vertical Migration Capability Across Arria® V Device Packages and DensitiesThe arrows indicate the vertical migration paths. Some packages have several migration paths. The devices included in each vertical migration path are shaded. You can also migrate your design across device densities in the same package option if the devices have the same dedicated pins, configuration pins, and power pins.


You can achieve the vertical migration shaded in red if you use only up to 320 GPIOs, up to nine 6 Gbps transceiver channels, and up to four 10 Gbps transceiver (for Arria V GT devices). This migration path is not shown in the Intel® Quartus® Prime software Pin Migration View.

Note: To verify the pin migration compatibility, use the Pin Migration View window in the Intel® Quartus® Prime software Pin Planner.
Note: Except for Arria V GX A5 and A7, and Arria V GT C7 devices, all other Arria V GX and GT devices require a specific power-up sequence. If you plan to migrate your design from Arria V GX A5 and A7, and Arria V GT C7 devices to other Arria V devices, your design must adhere to the same required power-up sequence.

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