Arria V Device Overview

ID 683440
Date 11/20/2020
Public
Document Table of Contents

1.3.5.3. Package Plan

Table 13.  Package Plan for Arria® V ST Devices The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.

Member Code

F896

(31 mm)

F1152

(35 mm)

F1517

(40 mm)

FPGA GPIO HPS I/O XCVR FPGA GPIO HPS I/O XCVR FPGA GPIO HPS I/O XCVR
6 Gbps 10 Gbps 6 Gbps 10 Gbps 6 Gbps 10 Gbps
D3 250 208 12 6 385 208 18 8 540 208 30 16
D5 250 208 12 6 385 208 18 8 540 208 30 16

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