Arria® V Device Overview

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ID 683440
Date 11/20/2020
Public
Document Table of Contents
Document Table of Contents x
1. Arria V Device Overview
1. Arria V Device Overview x
1.1. Key Advantages of Arria® V Devices 1.2. Summary of Arria® V Features 1.3. Arria® V Device Variants and Packages 1.4. I/O Vertical Migration for Arria® V Devices 1.5. Adaptive Logic Module 1.6. Variable-Precision DSP Block 1.7. Embedded Memory Blocks 1.8. Clock Networks and PLL Clock Sources 1.9. FPGA General Purpose I/O 1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP 1.11. External Memory Interface 1.12. Low-Power Serial Transceivers 1.13. SoC with HPS 1.14. Dynamic Reconfiguration 1.15. Enhanced Configuration and Configuration via Protocol 1.16. Power Management 1.17. Document Revision History
1.3. Arria® V Device Variants and Packages x
1.3.1. Arria V GX 1.3.2. Arria V GT 1.3.3. Arria V GZ 1.3.4. Arria V SX 1.3.5. Arria V ST
1.3.1. Arria V GX x
1.3.1.1. Available Options 1.3.1.2. Maximum Resources 1.3.1.3. Package Plan
1.3.2. Arria V GT x
1.3.2.1. Available Options 1.3.2.2. Maximum Resources 1.3.2.3. Package Plan
1.3.3. Arria V GZ x
1.3.3.1. Available Options 1.3.3.2. Maximum Resources 1.3.3.3. Package Plan
1.3.4. Arria V SX x
1.3.4.1. Available Options 1.3.4.2. Maximum Resources 1.3.4.3. Package Plan
1.3.5. Arria V ST x
1.3.5.1. Available Options 1.3.5.2. Maximum Resources 1.3.5.3. Package Plan
1.7. Embedded Memory Blocks x
1.7.1. Types of Embedded Memory 1.7.2. Embedded Memory Capacity in Arria V Devices 1.7.3. Embedded Memory Configurations
1.11. External Memory Interface x
1.11.1. Hard and Soft Memory Controllers 1.11.2. External Memory Performance 1.11.3. HPS External Memory Performance
1.12. Low-Power Serial Transceivers x
1.12.1. Transceiver Channels 1.12.2. PMA Features 1.12.3. PCS Features
1.13. SoC with HPS x
1.13.1. HPS Features 1.13.2. FPGA Configuration and Processor Booting 1.13.3. Hardware and Software Development
1.13.1. HPS Features x
1.13.1.1. System Peripherals and Debug Access Port 1.13.1.2. HPS–FPGA AXI Bridges 1.13.1.3. HPS SDRAM Controller Subsystem
1.14. Dynamic Reconfiguration x
1.14.1. Dynamic Reconfiguration
1. Arria V Device Overview

1.2. Summary of Arria® V Features

Table 2.  Summary of Features for Arria® V Devices
Feature Description

Technology

  • TSMC's 28-nm process technology:
    • Arria® V GX, GT, SX, and ST—28-nm low power (28LP) process
    • Arria® V GZ—28-nm high performance (28HP) process
  • Lowest static power in its class (less than 1.2 W for 500K logic elements (LEs) at 85°C junction under typical conditions)
  • 0.85 V, 1.1 V, or 1.15 V core nominal voltage

Packaging

  • Thermal composite flip chip BGA packaging
  • Multiple device densities with identical package footprints for seamless migration between different device densities
  • Leaded1, lead-free (Pb-free), and RoHS-compliant options

High-performance FPGA fabric

  • Enhanced 8-input ALM with four registers
  • Improved routing architecture to reduce congestion and improve compilation time

Internal memory blocks

  • M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC) ( Arria® V GX, GT, SX, and ST devices only)
  • M20K—20-Kb memory blocks with hard ECC ( Arria® V GZ devices only)
  • Memory logic array block (MLAB)-640-bit distributed LUTRAM where you can use up to 50% of the ALMs as MLAB memory

Embedded Hard IP blocks

Variable-precision DSP

  • Native support for up to four signal processing precision levels:
    • Three 9 x 9, two 18 x 18, or one 27 x 27 multiplier in the same variable-precision DSP block
    • One 36 x 36 multiplier using two variable-precision DSP blocks ( Arria® V GZ devices only)
  • 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)
  • Embedded internal coefficient memory
  • Preadder/subtractor for improved efficiency

Memory controller

( Arria® V GX, GT, SX, and ST only)

DDR3 and DDR2

Embedded transceiver I/O

  • Custom implementation:
    • Arria® V GX and SX devices—up to 6.5536 Gbps
    • Arria® V GT and ST devices—up to 10.3125 Gbps
    • Arria® V GZ devices—up to 12.5 Gbps
  • PCI Express® (PCIe®) Gen2 (x1, x2, or x4) and Gen1 (x1, x2, x4, or x8) hard IP with multifunction support, endpoint, and root port
  • PCIe Gen3 (x1, x2, x4, or x8) support ( Arria® V GZ only)
  • Gbps Ethernet (GbE) and XAUI physical coding sublayer (PCS)
  • Common Public Radio Interface (CPRI) PCS
  • Gigabit-capable passive optical network (GPON) PCS
  • 10-Gbps Ethernet (10GbE) PCS ( Arria® V GZ only)
  • Serial RapidIO® (SRIO) PCS
  • Interlaken PCS ( Arria® V GZ only)

Clock networks

  • Up to 650 MHz global clock network
  • Global, quadrant, and peripheral clock networks
  • Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops (PLLs)

  • High-resolution fractional PLLs
  • Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
  • Integer mode and fractional mode
  • LC oscillator ATX transmitter PLLs ( Arria® V GZ only)

FPGA General-purpose I/Os (GPIOs)

  • 1.6 Gbps LVDS receiver and transmitter
  • 800 MHz/1.6 Gbps external memory interface
  • On-chip termination (OCT)
  • 3.3 V support 2

External Memory Interface

Memory interfaces with low latency:

  • Hard memory controller-up to 1.066 Gbps
  • Soft memory controller-up to 1.6 Gbps

Low-power high-speed serial interface

  • 600 Mbps to 12.5 Gbps integrated transceiver speed
  • Less than 105 mW per channel at 6 Gbps, less than 165 mW per channel at 10 Gbps, and less than 170 mW per channel at 12.5 Gbps
  • Transmit pre-emphasis and receiver equalization
  • Dynamic partial reconfiguration of individual channels
  • Physical medium attachment (PMA) with soft PCS that supports 9.8304 Gbps CPRI ( Arria® V GT and ST only)
  • PMA with hard PCS that supports up to 9.8 Gbps CPRI ( Arria® V GZ only)
  • Hard PCS that supports 10GBASE-R and 10GBASE-KR ( Arria® V GZ only)

HPS

( Arria® V SX and ST devices only)

  • Dual-core ARM Cortex-A9 MPCore processor—up to 1.05 GHz maximum frequency with support for symmetric and asymmetric multiprocessing
  • Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO interfaces
  • System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA) controller, FPGA configuration manager, and clock and reset managers
  • On-chip RAM and boot ROM
  • HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa
  • FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport front end (MPFE) of the HPS SDRAM controller
  • ARM CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

Configuration

  • Tamper protection-comprehensive design protection to protect your valuable IP investments
  • Enhanced advanced encryption standard (AES) design security features
  • CvP
  • Dynamic reconfiguration of the FPGA
  • Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8, x16, and x32 ( Arria® V GZ) configuration options
  • Remote system upgrade
1 Contact Intel for availability.
2 Arria® V GZ devices support 3.3 V with a 3.0 V VCCIO.
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