Arria V Device Overview

ID 683440
Date 11/20/2020
Document Table of Contents

1.12.2. PMA Features

To prevent core and I/O noise from coupling into the transceivers, the PMA block is isolated from the rest of the chip—ensuring optimal signal integrity. For the transceivers, you can use the channel PLL of an unused receiver PMA as an additional transmit PLL.

Table 20.  PMA Features of the Transceivers in Arria V Devices
Features Capability
Backplane support
  • Arria V GX, GT, SX, and ST devices—Driving capability at 6.5536 Gbps with up to 25 dB channel loss
  • Arria V GZ devices—Driving capability at 12.5 Gbps with up to 16 dB channel loss
Chip-to-chip support
  • Arria V GX, GT, SX, and ST devices—Up to 10.3125 Gbps
  • Arria V GZ devices—Up to 12.5 Gbps
PLL-based clock recovery Superior jitter tolerance
Programmable serializer and deserializer (SERDES) Flexible SERDES width
Equalization and pre-emphasis
  • Arria V GX, GT, SX, and ST devices—Up to 14.37 dB of pre-emphasis and up to 4.7 dB of equalization
  • Arria V GZ devices—4-tap pre-emphasis and de-emphasis
Ring oscillator transmit PLLs 611 Mbps to 10.3125 Gbps

LC oscillator ATX transmit PLLs

(Arria V GZ devices only)

600 Mbps to 12.5 Gbps
Input reference clock range 27 MHz to 710 MHz
Transceiver dynamic reconfiguration Allows the reconfiguration of a single channel without affecting the operation of other channels