1.1. Key Advantages of Arria® V Devices
1.2. Summary of Arria® V Features
1.3. Arria® V Device Variants and Packages
1.4. I/O Vertical Migration for Arria® V Devices
1.5. Adaptive Logic Module
1.6. Variable-Precision DSP Block
1.7. Embedded Memory Blocks
1.8. Clock Networks and PLL Clock Sources
1.9. FPGA General Purpose I/O
1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP
1.11. External Memory Interface
1.12. Low-Power Serial Transceivers
1.13. SoC with HPS
1.14. Dynamic Reconfiguration
1.15. Enhanced Configuration and Configuration via Protocol
1.16. Power Management
1.17. Document Revision History
1.13. SoC with HPS
Each SoC combines an FPGA fabric and an HPS in a single device. This combination delivers the flexibility of programmable logic with the power and cost savings of hard IP in these ways:
- Reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor
- Allows you to differentiate the end product in both hardware and software, and to support virtually any interface standard
- Extends the product life and revenue through in-field hardware and software updates