Arria V Device Overview

ID 683440
Date 11/20/2020
Public
Document Table of Contents

1.13. SoC with HPS

Each SoC combines an FPGA fabric and an HPS in a single device. This combination delivers the flexibility of programmable logic with the power and cost savings of hard IP in these ways:

  • Reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor
  • Allows you to differentiate the end product in both hardware and software, and to support virtually any interface standard
  • Extends the product life and revenue through in-field hardware and software updates

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