1.16. Power Management
Leveraging the FPGA architectural features, process technology advancements, and transceivers that are designed for power efficiency, the Arria® V devices consume less power than previous generation Arria® V FPGAs:
- Total device core power consumption—less by up to 50%.
- Transceiver channel power consumption—less by up to 50%.
Additionally, Arria® V devices contain several hard IP blocks, including PCIe Gen1, Gen2, and Gen3, GbE, SRIO, GPON, and CPRI protocols, that reduce logic resources and deliver substantial power savings of up to 25% less power than equivalent soft implementations.
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