Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Public
Document Table of Contents
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1. Transceiver Architecture in Arria V Devices

Describes the Arria® V transceiver architecture, channels, and transmitter and receiver channel datapaths.

Altera® 28-nm Arria® V FPGAs provide integrated transceivers with the lowest power requirement at 12.5-, 10-, and 6-Gigabits per second (Gbps). These transceivers comply with a wide range of protocols and data rate standards.

Table 1.  Arria V Variants
Variants Hard Processor System (HPS) Up to 6.5536 Gbps Beyond 6.5536 Gbps
GX N/A Backplane N/A
GT N/A Backplane N/A
GZ N/A Backplane Up to 12.5 Gbps with backplane support
SX Yes Backplane N/A
ST Yes Backplane N/A