Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

2.1.3. Fractional PLL (fPLL)

The fPLL clock output can be used as input reference clock source to transmitter PLL or CDR.

Cascading the fPLL to transmitter PLL or CDR enables you to use an input reference clock that is not supported by the transmitter PLL or CDR. The fPLL synthesizes a supported input reference clock for the transmitter PLL or CDR.

A fPLL is available for each group of three transceiver channels. Each fPLL drives one of two fPLL cascade clock network lines that can provide an input reference clock to any transmitter PLL or CDR on the same side of a device.

Note: An fPLL can also be used as a transmit PLL.
Figure 46. fPLL Clock Output as Input Reference Clock

Note: It is not recommended to use a fractional PLL in fractional mode for transceiver applications as a TX PLL or for PLL cascading.
Note: Transceiver associated power pins must be powered up. If a dedicated transceiver refclk pin is used as a clock reference for a core fractional PLL, then at least one transceiver must be instantiated in the design.