Arria® V Device Handbook: Volume 2: Transceivers

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ID 683573
Date 5/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Transceiver Architecture in Arria V Devices 2. Transceiver Clocking in Arria V Devices 3. Transceiver Reset Control in Arria V Devices 4. Transceiver Protocol Configurations in Arria V Devices 5. Transceiver Custom Configurations in Arria V Devices 6. Transceiver Configurations in Arria V GZ Devices 7. Transceiver Loopback Support in Arria V Devices 8. Dynamic Reconfiguration in Arria V Devices
1. Transceiver Architecture in Arria V Devices x
1.1. Architecture Overview 1.2. PCS Architecture 1.3. Channel Bonding 1.4. PLL Sharing 1.5. Document Revision History
1.1. Architecture Overview x
1.1.1. Transceiver Banks 1.1.2. 10-Gbps Support Capability in GT and ST Devices 1.1.3. Transceiver Channel Architecture 1.1.4. PMA Architecture
1.1.2. 10-Gbps Support Capability in GT and ST Devices x
1.1.2.1. Enhanced Small Form-Factor Pluggable (SFP+) Interface 1.1.2.2. 10GBASE-KR Support 1.1.2.3. 9.8 Gbps CPRI Application
1.1.4. PMA Architecture x
1.1.4.1. Transmitter PMA Datapath 1.1.4.2. Receiver PMA Datapath 1.1.4.3. Transmitter PLL 1.1.4.4. Clock Divider 1.1.4.5. Calibration Block
1.1.4.1. Transmitter PMA Datapath x
1.1.4.1.1. Serializer 1.1.4.1.2. Transmitter Buffer
1.1.4.2. Receiver PMA Datapath x
1.1.4.2.1. Receiver Buffer 1.1.4.2.2. Channel PLL 1.1.4.2.3. Deserializer
1.1.4.3. Transmitter PLL x
1.1.4.3.1. Auxiliary Transmit (ATX) PLL Architecture 1.1.4.3.2. CMU PLL 1.1.4.3.3. fPLL as Transmitter PLL
1.1.4.5. Calibration Block x
1.1.4.5.1. Offset Cancellation in the Receiver Buffer and Receiver CDR 1.1.4.5.2. ATX PLL Calibration for Arria V GZ Devices 1.1.4.5.3. Calibration Block Boundary
1.2. PCS Architecture x
1.2.1. Transmitter PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ Standard PCS 1.2.2. Receiver PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ Standard PCS 1.2.3. 10G PCS Architecture for Arria V GZ Devices 1.2.4. PCIe Gen3 PCS Architecture
1.2.1. Transmitter PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ Standard PCS x
1.2.1.1. Transmitter Phase Compensation FIFO 1.2.1.2. Byte Serializer 1.2.1.3. 8B/10B Encoder 1.2.1.4. Transmitter Bit-Slip
1.2.1.1. Transmitter Phase Compensation FIFO x
1.2.1.1.1. Phase Compensation Mode 1.2.1.1.2. Registered Mode
1.2.1.3. 8B/10B Encoder x
1.2.1.3.1. 8B/10B Encoder in Single-Width Mode 1.2.1.3.2. 8B/10B Encoder in Double-Width Mode 1.2.1.3.3. Running Disparity Control 1.2.1.3.4. Encoder Output During Reset Sequence
1.2.2. Receiver PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ Standard PCS x
1.2.2.1. Word Aligner 1.2.2.2. Rate Match FIFO 1.2.2.3. 8B/10B Decoder 1.2.2.4. Byte Deserializer 1.2.2.5. Byte Ordering 1.2.2.6. Receiver Phase Compensation FIFO
1.2.2.1. Word Aligner x
1.2.2.1.1. Word Aligner in Manual Alignment Mode 1.2.2.1.2. Bit-Slip Mode 1.2.2.1.3. Word Aligner in Automatic Synchronization State Machine Mode 1.2.2.1.4. Word Aligner in Deterministic Latency State Machine Mode 1.2.2.1.5. Programmable Run-Length Violation Detection 1.2.2.1.6. Receiver Polarity Inversion 1.2.2.1.7. Bit Reversal 1.2.2.1.8. Receiver Byte Reversal
1.2.2.3. 8B/10B Decoder x
1.2.2.3.1. 8B/10B Decoder in Single-Width Mode 1.2.2.3.2. 8B/10B Decoder in Double-Width Mode
1.2.2.5. Byte Ordering x
1.2.2.5.1. Byte Ordering in Single-Width Mode 1.2.2.5.2. Byte Ordering in Double-Width Mode 1.2.2.5.3. Word Aligner-Based Ordering Mode 1.2.2.5.4. Manual Ordering Mode
1.2.2.6. Receiver Phase Compensation FIFO x
1.2.2.6.1. Phase Compensation Mode 1.2.2.6.2. Registered Mode
1.2.3. 10G PCS Architecture for Arria V GZ Devices x
1.2.3.1. Transmitter 10G PCS Datapath 1.2.3.2. Receiver 10G PCS Datapath
1.2.3.1. Transmitter 10G PCS Datapath x
1.2.3.1.1. Transmitter FIFO 1.2.3.1.2. Frame Generator 1.2.3.1.3. CRC-32 Generator 1.2.3.1.4. 64B/66B Encoder 1.2.3.1.5. Scrambler 1.2.3.1.6. Disparity Generator 1.2.3.1.7. Transmitter Gearbox
1.2.3.2. Receiver 10G PCS Datapath x
1.2.3.2.1. Receiver Gearbox 1.2.3.2.2. Block Synchronizer 1.2.3.2.3. Disparity Checker 1.2.3.2.4. Descrambler 1.2.3.2.5. Frame Synchronizer 1.2.3.2.6. Bit-Error Rate (BER) Monitor 1.2.3.2.7. 64B/66B Decoder 1.2.3.2.8. CRC-32 Checker 1.2.3.2.9. Receiver FIFO
1.2.4. PCIe Gen3 PCS Architecture x
1.2.4.1. Transmitter PCIe Gen3 PCS Datapath 1.2.4.2. Receiver PCIe Gen3 PCS Datapath 1.2.4.3. PIPE Interface
1.2.4.1. Transmitter PCIe Gen3 PCS Datapath x
1.2.4.1.1. Phase Compensation FIFO (Shared with Standard PCS) 1.2.4.1.2. Scrambler 1.2.4.1.3. Encoder 1.2.4.1.4. Gearbox
1.2.4.2. Receiver PCIe Gen3 PCS Datapath x
1.2.4.2.1. Block Sync 1.2.4.2.2. Rate Match FIFO 1.2.4.2.3. Decoder 1.2.4.2.4. Descrambler
1.2.4.3. PIPE Interface x
1.2.4.3.1. Auto Speed Negotiation Block 1.2.4.3.2. Electrical Idle Inference Block 1.2.4.3.3. Clock Data Recovery (CDR) Control Block
1.3. Channel Bonding x
1.3.1. Bonded Channel Configurations 1.3.2. Non-Bonded Channel Configurations
2. Transceiver Clocking in Arria V Devices x
2.1. Input Reference Clocking 2.2. Internal Clocking 2.3. FPGA Fabric–Transceiver Interface Clocking 2.4. Document Revision History
2.1. Input Reference Clocking x
2.1.1. Reference Clock Network 2.1.2. Dual-Purpose RX/refclk Pin 2.1.3. Fractional PLL (fPLL)
2.2. Internal Clocking x
2.2.1. Transmitter Clock Network 2.2.2. Transmitter Clocking 2.2.3. Receiver Clocking
2.2.2. Transmitter Clocking x
2.2.2.1. Non-Bonded Channel Configurations 2.2.2.2. Bonded Channel Configurations
2.2.3. Receiver Clocking x
2.2.3.1. Receiver Non-Bonded Channel Configurations 2.2.3.2. Receiver Bonded Channel Configurations
2.3. FPGA Fabric–Transceiver Interface Clocking x
2.3.1. Transceiver Datapath Interface Clocking 2.3.2. Transmitter Datapath Interface Clocking 2.3.3. Receiver Datapath Interface Clock 2.3.4. GXB 0 PPM Core Clock Assignment for GZ Devices
2.3.2. Transmitter Datapath Interface Clocking x
2.3.2.1. Quartus II-Software Selected Transmitter Datapath Interface Clock 2.3.2.2. Selecting a Transmitter Datapath Interface Clock
2.3.3. Receiver Datapath Interface Clock x
2.3.3.1. Quartus II Software-Selected Receiver Datapath Interface Clock 2.3.3.2. Selecting a Receiver Datapath Interface Clock
3. Transceiver Reset Control in Arria V Devices x
3.1. PHY IP Embedded Reset Controller 3.2. User-Coded Reset Controller 3.3. Transceiver Reset Using Avalon Memory Map Registers 3.4. Clock Data Recovery in Manual Lock Mode Resetting the Transceiver During Dynamic Reconfiguration 3.6. Transceiver Blocks Affected by the Reset and Powerdown Signals 3.7. Transceiver Power-Down 3.8. Document Revision History
3.1. PHY IP Embedded Reset Controller x
3.1.1. Embedded Reset Controller Signals 3.1.2. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Power-Up 3.1.3. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Operation
3.2. User-Coded Reset Controller x
3.2.1. User-Coded Reset Controller Signals 3.2.2. Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up 3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation 3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration 3.2.5. Resetting the Receiver with the User-Coded Reset Controller During Device Operation
3.3. Transceiver Reset Using Avalon Memory Map Registers x
3.3.1. Transceiver Reset Control Signals Using Avalon Memory Map Registers
3.4. Clock Data Recovery in Manual Lock Mode x
3.4.1. Control Settings for CDR Manual Lock Mode 3.4.2. Resetting the Transceiver in CDR Manual Lock Mode
4. Transceiver Protocol Configurations in Arria V Devices x
4.1. PCI Express 4.2. Gigabit Ethernet 4.3. XAUI 4.4. 10GBASE-R 4.5. Serial Digital Interface 4.6. Gigabit-Capable Passive Optical Network (GPON) 4.7. Serial Data Converter (SDC) JESD204 4.8. SATA and SAS Protocols 4.9. Deterministic Latency Protocols—CPRI and OBSAI 4.10. Serial RapidIO 4.11. Document Revision History
4.1. PCI Express x
4.1.1. PCIe Transceiver Datapath 4.1.2. PCIe Supported Features 4.1.3. PIPE Transceiver Channel Placement Guidelines 4.1.4. PCIe Supported Configurations and Placement Guidelines 4.1.5. PIPE Transceiver Clocking
4.1.2. PCIe Supported Features x
4.1.2.1. PIPE Interface 4.1.2.2. Transmitter Electrical Idle Generation 4.1.2.3. Power State Management 4.1.2.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support 4.1.2.5. Receiver Status 4.1.2.6. Receiver Detection 4.1.2.7. Clock Rate Compensation Up to ±300 ppm 4.1.2.8. PCIe Reverse Parallel Loopback
4.2. Gigabit Ethernet x
4.2.1. Gigabit Ethernet Transceiver Datapath
4.3. XAUI x
4.3.1. Transceiver Datapath in a XAUI Configuration 4.3.2. XAUI Supported Features 4.3.3. Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration
4.4. 10GBASE-R x
4.4.1. 10GBASE-R Transceiver Datapath Configuration 4.4.2. 10GBASE-R Supported Features 4.4.3. 10GBASE-R Transceiver Clocking
4.5. Serial Digital Interface x
4.5.1. Configurations Supported in SDI Mode 4.5.2. Serial Digital Interface Transceiver Datapath
4.9. Deterministic Latency Protocols—CPRI and OBSAI x
4.9.1. Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode 4.9.2. Channel PLL Feedback for Deterministic Relationship 4.9.3. CPRI and OBSAI 4.9.4. CPRI Enhancements
5. Transceiver Custom Configurations in Arria V Devices x
5.1. Standard PCS Configuration 5.2. Standard PCS in Low Latency Configuration 5.3. PMA Direct 5.4. Document Revision History
5.1. Standard PCS Configuration x
5.1.1. Custom Configuration Channel Options 5.1.2. Rate Match FIFO in Custom Configuration
5.1.2. Rate Match FIFO in Custom Configuration x
5.1.2.1. Rate Match FIFO Behaviors in Custom Single-Width Mode 5.1.2.2. Rate Match FIFO Behaviors in Custom Double-Width Mode
5.2. Standard PCS in Low Latency Configuration x
5.2.1. Low Latency Custom Configuration Channel Options
6. Transceiver Configurations in Arria V GZ Devices x
6.1. 10GBASE-R and 10GBASE-KR 6.2. Interlaken 6.3. PCI Express (PCIe)—Gen1, Gen2, and Gen3 6.4. XAUI 6.5. CPRI and OBSAI—Deterministic Latency Protocols 6.6. Transceiver Configurations 6.7. Native PHY IP Configuration 6.8. Document Revision History
6.1. 10GBASE-R and 10GBASE-KR x
6.1.1. 10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration 6.1.2. 10GBASE-R and 10GBASE-KR Supported Features 6.1.3. 1000BASE-X and 1000BASE-KX Transceiver Datapath 6.1.4. 1000BASE-X and 1000BASE-KX Supported Features 6.1.5. Synchronization State Machine Parameters in 1000BASE-X and 1000BASE-KX Configurations 6.1.6. Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX Configurations
6.2. Interlaken x
6.2.1. Transceiver Datapath Configuration 6.2.2. Supported Features 6.2.3. Transceiver Clocking
6.3. PCI Express (PCIe)—Gen1, Gen2, and Gen3 x
6.3.1. Transceiver Datapath Configuration 6.3.2. Supported Features for PCIe Configurations 6.3.3. Supported Features for PCIe Gen3 6.3.4. Transceiver Clocking and Channel Placement Guidelines 6.3.5. Advanced Channel Placement Guidelines for PIPE Configurations 6.3.6. Transceiver Clocking for PCIe Gen3
6.4. XAUI x
6.4.1. Transceiver Datapath in a XAUI Configuration 6.4.2. Supported Features 6.4.3. Transceiver Clocking and Channel Placement Guidelines
6.5. CPRI and OBSAI—Deterministic Latency Protocols x
6.5.1. Transceiver Datapath Configuration 6.5.2. Phase Compensation FIFO in Register Mode 6.5.3. Channel PLL Feedback 6.5.4. CPRI and OBSAI
6.6. Transceiver Configurations x
6.6.1. Standard PCS Configurations—Custom Datapath 6.6.2. Standard PCS Configurations—Low Latency Datapath 6.6.3. Transceiver Channel Placement Guidelines 6.6.4. 10G PCS Configurations 6.6.5. Merging Instances
6.6.4. 10G PCS Configurations x
6.6.4.1. 10G PCS Datapath Functionality 6.6.4.2. Using the coreclkin Ports
6.7. Native PHY IP Configuration x
6.7.1. Protocols and Transceiver PHY IP Support 6.7.2. Native PHY Transceiver Datapath Configuration 6.7.3. Standard PCS Features 6.7.4. 10G PCS Supported Features 6.7.5. 10G Datapath Configurations with Native PHY IP 6.7.6. PMA Direct Supported Features 6.7.7. Channel and PCS Datapath Dynamic Switching Reconfiguration
6.7.3. Standard PCS Features x
6.7.3.1. Standard PCS Receiver and Transmitter Blocks
6.7.4. 10G PCS Supported Features x
6.7.4.1. 10G PCS Receiver and Transmitter Blocks 6.7.4.2. Receiver and Transmit Gearbox in Native PHY IP
7. Transceiver Loopback Support in Arria V Devices x
7.1. Serial Loopback 7.2. Forward Parallel Loopback 7.3. PIPE Reverse Parallel Loopback 7.4. Reverse Serial Loopback 7.5. Reverse Serial Pre-CDR Loopback 7.6. Document Revision History
8. Dynamic Reconfiguration in Arria V Devices x
8.1. Dynamic Reconfiguration Features 8.2. Offset Cancellation 8.3. Transmitter Duty Cycle Distortion Calibration 8.4. PMA Analog Controls Reconfiguration 8.5. Dynamic Reconfiguration of Loopback Modes 8.6. Transceiver PLL Reconfiguration 8.7. Transceiver Channel Reconfiguration 8.8. Transceiver Interface Reconfiguration 8.9. Reduced .mif Reconfiguration 8.10. On-Chip Signal Quality Monitoring (Eye Viewer) 8.11. Adaptive Equalization 8.12. Decision Feedback Equalization 8.13. Unsupported Reconfiguration Modes 8.14. Document Revision History
1. Transceiver Architecture in Arria V Devices
2. Transceiver Clocking in Arria V Devices
3. Transceiver Reset Control in Arria V Devices
4. Transceiver Protocol Configurations in Arria V Devices
5. Transceiver Custom Configurations in Arria V Devices
6. Transceiver Configurations in Arria V GZ Devices
7. Transceiver Loopback Support in Arria V Devices
8. Dynamic Reconfiguration in Arria V Devices

6.7.1. Protocols and Transceiver PHY IP Support

Table 85.  Protocols and PHY IP Features Support
Protocol Standard Transceiver IP PCS Type Avalon-MM Register Interface Reset Controller
PCIe Gen3 x1, x2, x4, x8 PHY IP Core for PCIe (PIPE) 41 Standard and Gen3 Yes Embedded
PCIe Gen2 x1, x2, x4, x8 PHY IP Core for PCIe (PIPE) 41 Standard Yes Embedded
PCIe Gen1 x1, x2, x4, x8 PHY IP Core for PCIe (PIPE) 41 Standard Yes Embedded
10GBASE-R 10GBASE-R 10G Yes Embedded
Native PHY 10G No External Reset IP
10G/40G Ethernet Native PHY 10G No External Reset IP
1G/10Gb Ethernet 1G/10GbE and 10GBASE-KR Standard and 10G Yes Embedded
1G/10Gb Ethernet with 1588 1G/10GbE and 10GBASE-KR Standard and 10G Yes Embedded
10G Ethernet with 1588 Native PHY 10G No External Reset IP
10GBASE-KR and 1000BASE-X 1G/10GbE and 10GBASE-KR Standard and 10G Yes Embedded
1000BASE-X and SGMII Gigabit Ethernet Custom PHY Standard Standard Yes Embedded or External Reset IP
XAUI XAUI PHY IP Standard Soft-PCS Yes Embedded
SPAUI Low Latency PHY Standard and 10G Yes Embedded or External Reset IP
Native PHY Standard and 10G No External Reset IP
DDR XAUI Low Latency PHY Standard and 10G Yes Embedded or External Reset IP
Native PHY Standard and 10G No External Reset IP
Interlaken (CEI-6G/11G) Interlaken PHY 10G Yes Embedded
Native PHY 42 10G No External Reset IP
OTU-3 (40G) via OIF SFI-5.2/SFI-5.1 Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
OTU-2 (10G) via OIF SFI-5.1s Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
OTU-1 (2.7G) Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
SONET/SDH STS-768/STM-256 (40G) via OIF SFI-5.2 Low Latency PHY 10G Yes Embedded or External Reset IP
Low Latency PHY Standard Yes Embedded or External Reset IP
SONET/SDH STS-768/STM-256 (40G) via OIF SFI-5.2/SFI-5.1 Native PHY Standard and 10G No External Reset IP
SONET/SDH STS-192/STM-64 (10G) via SFP+/SFF-8431/ CEI-11G Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
SONET/SDH STS-192/STM-64 (10G) via OIF SFI-5.1s/SxI-5/ SFI-4.2 Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
SONET STS-96 (5G) via OIF SFI-5.1s Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
SONET/SDH STS-48/STM-16 (2.5G) via SFP/TFI-5.1 Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
SONET/SDH STS-12/STM-4 (0.622G) via SFP/TFI-5.1 Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
Intel QPI Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY PMA-Direct No External Reset IP
10G SDI Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
SD-SDI/HD-SDI/ 3G-SDI Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
10G GPON/EPON Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
GPON/EPON Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
10G Fibre Channel Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
8G/4G Fibre Channel Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
FDR/FDR-10 Infiniband x1, x4, x12 Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
SDR/DDR/QDR Infiniband x1, x4, x12 Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
CPRI 4.2/OBSAI RP3 v4.2 Deterministic PHY Standard Yes Embedded
Native PHY Standard No External Reset IP
SRIO 2.2/1.3 43 Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
SATA 3.0/2.0/1.0 and SAS 2.0/1.0 Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
HiGig+/2+ Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
JESD204A Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
ASI Custom PHY Standard Yes Embedded or External Reset IP
SPI 5 (50G) Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
Custom and other protocols Native PHY Standard, 10G, and PMA-Direct No External Reset IP
41 Hard IP for PCI Express is also available as a Intel® FPGA IP core function.
42 A Soft-PCS bonding IP is required.
43 Nx Multi-Alignment Deskew State Machine must be implemented in the core.
Level Two Title