Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

1.1. Architecture Overview

Figure 1. Basic Layout of Transceivers in Arria V Devices

The Arria V hard IP for PCIe implements the PCIe protocol stack including the following layers:

  • Physical interface/media access control (PHY/MAC) layer
  • Data link layer
  • Transaction layer

The embedded hard IP saves significant FPGA resources, reduces design risk, and reduces the time required to achieve timing closure. The hard IP complies with the PCI Express Base Specification 1.1, 2.0, and 3.0 for Gen1, Gen2, and Gen3 signaling data rates, respectively. In addition, the Arria V GZ variant supports PCI Express Base Specification 3.0 for Gen3 signaling datarates.