Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

1.2.2. Receiver PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ Standard PCS

Table 21.  Functional Blocks in the Arria V GX/GT/SX/ST 6-Gbps Receiver PCS and Arria V GZ Standard PCS Datapaths
Block Functionality
Word Aligner
  • Searches for a predefined alignment pattern in the deserialized data to identify the correct boundary and restores the word boundary during link synchronization
  • Supports an alignment pattern length of 7, 8, 10, 16, 20, or 32 bits
  • Supports operation in four modes—manual alignment, bit-slip, automatic synchronization state machine, and deterministic latency state machine—in single- and double-width configurations
  • Supports the optional programmable run-length violation detection, polarity inversion, bit reversal, and byte reversal features
Rate Match FIFO
  • Compensates for small clock frequency differences of up to ±300 ppm—600 ppm total—between the upstream transmitter and the local receiver clocks by inserting or deleting skip symbols when necessary
  • Supports operation that is compliant to the clock rate compensation function in supported protocols
8B/10B Decoder
  • Receives 10-bit data and decodes the data into an 8-bit data and a 1-bit control identifier—in compliance with Clause 36 of the IEEE 802.3 specification
  • Supports operation in single- and double-width modes
Byte Deserializer
  • Divides the FPGA fabric–transceiver interface frequency in half at the receiver channel by doubling the receiver output datapath width
  • Allows the receiver channel to operate at higher data rates with the FPGA fabric–transceiver interface frequency that is within the maximum limit
  • Supports operation in double-width modes
Byte Ordering
  • Searches for a predefined pattern that must be ordered to the LSByte position in the parallel data going to the FPGA fabric when you enable the byte deserializer
Receiver Phase Compensation FIFO
  • Compensates for the phase difference between the low-speed parallel clock and the FPGA fabric interface clock when interfacing the receiver PCS with the FPGA fabric directly or with the PCIe hard IP block
  • Supports operation in phase compensation and registered modes