Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Receiver Buffer

The receiver input buffer receives serial data from the rx_serial_data port and feeds the serial data to the channel PLL configured as a CDR PLL.

Figure 14. Receiver BufferChannel PLL configured as a CDR.

Modifying programmable values within receiver input buffers can be performed by a single reconfiguration controller for the entire FPGA, or multiple reconfiguration controllers if desired. Within each transceiver bank a maximum of two reconfiguration controllers is allowed; one for the three-transceiver triplet in the upper-half of the bank, and one for the lower-half. This is due to a single slave interface to all PLLs and PMAs within each triplet. Therefore, many triplets can be connected to a single reconfiguration controller, but only one reconfiguration controller can be connected to the three transceivers within any triplet.

Note: A maximum of one reconfiguration controller is allowed per transceiver bank upper-half or lower-half triplet.

Receiver Analog Settings

Arria V GZ channels have two receiver analog modes: half-bandwidth and full-bandwidth. The half-bandwidth data rate is up to 6.25 Gbps; the full-bandwidth data rate is from 6.25 Gbps to 12.5 Gbps. You can select which mode to use in the Assignment Editor of the Quartus II software (Receiver Equalizer Gain Bandwidth Select).

Table 12.  Arria V Receiver Buffer Features
Category Features Description
Improve Signal Integrity Programmable CTLE (Continuous Time Linear Equalization) Boosts the high-frequency components of the received signal, which may be attenuated when propagating through the transmission medium. The physical transmission medium can be represented as a low-pass filter in the frequency domain. Variation in the signal frequency response that is caused by attenuation leads to data-dependent jitter and other ISI effects, causing incorrect sampling on the input data at the receiver. The amount of the high-frequency boost required at the receiver to overcome signal attenuation depends on the loss characteristics of the physical medium.
Programmable DC Gain Provides equal boost to the received signal across the frequency spectrum.
Decision Feedback Equalization (DFE)

The decision feedback equalization feature consists of a 5-tap equalizer, which boosts the high frequency components of a signal without noise amplification by compensating for inter-symbol interference (ISI). There are two decision feedback equalization modes: manual and auto-adaptation.

The DFE is supported only in Arria V GZ devices.

EyeQ The EyeQ feature is a debug and diagnosis tool that helps you analyze the received data by measuring the horizontal and vertical eye opening.

The EyeQ is supported only in Arria V GZ devices, and not supported in Arria V GX, SX, ST and GT devices.

There are two multiplexers for the data and clock which select one path to feed to the deserializer.
Save Board Space and Cost On-Chip Biasing Establishes the required receiver common-mode voltage (RX VCM) level at the receiver input. The circuitry is available only if you enable OCT. When you disable OCT, you must implement off-chip biasing circuitry to establish the required RX VCM level.
Differential OCT The termination resistance is adjusted by the calibration circuitry, which compensates for the PVT. You can disable OCT and use external termination. However, you must implement off-chip biasing circuitry to establish the required RX VCM level. RX VCM is tri-stated when using external termination.
Reduce Power Programmable VCM Current Strength Controls the impedance of VCM. A higher impedance setting reduces current consumption from the on-chip biasing circuitry.
Note: There is no programmable option for Arria V GX, SX, GT and ST devices because only one VCM value is offered for AC coupled link in non-PCIe mode.
Protocol-Specific Function Signal Detect

Senses if the signal level present at the receiver input is above or below the threshold voltage that you specified. The detection circuitry has a hysteresis response that asserts the status signal only when a number of data pulses exceeding the threshold voltage are detected and deasserts the status signal when the signal level below the threshold voltage is detected for a number of recovered parallel clock cycles. The circuitry requires the input data stream to be 8B/10B-coded.

Signal detect is compliant to the threshold voltage and detection time requirements for electrical idle detection conditions as specified in the PCI Express Base Specification 2.0 for Gen1 and Gen2 signaling rates and PCI Express Base Specification 3.0 for Gen3 signaling rates (Arria V GZ only).

Figure 15. Receiver and EyeQ Architecture

The receiver can be AC- or DC-coupled to a transmitter. In an AC-coupled link, the AC-coupling capacitor blocks the transmitter VCM. At the receiver end, the termination and biasing circuitry restores the VCM level that is required by the receiver.

Figure 16. AC-Coupled Link with Arria V Receiver

When used in a DC-coupled link, the transmitter Vcm is fixed to 0.7V. The receiver Vcm is required to be at 0.7V. DC coupling is supported for serial data rates up to 3.2 Gbps.

You can DC-couple the Arria V GZ channel transmitter only to another Arria V GZ channel receiver for the entire datarate range from 600 Mbps to 12.5 Gbps so long as the same VCM value is observed.

Figure 17. DC-Coupled Link with Arria V Receiver

Continuous Time Linear Equalization (CTLE)

Each receiver buffer has five independently programmable equalization circuits that boost the high-frequency gain of the incoming signal, thereby compensating for the low-pass characteristics of the physical medium. The CTLE operates in two modes: manual mode and adaptive equalization (AEQ) mode

Manual Mode

Manual mode allows you to manually adjust the continuous time linear equalization to improve signal integrity. You can statically set the equalizer settings in the IP or you can dynamically change the equalizer settings with the reconfiguration controller IP.

Adaptive Equalization Mode

AEQ mode eliminates the need for manual tuning by enabling the Arria V device to automatically tune the receiver equalization settings based on the frequency content of the incoming signal and comparing that with internally generated reference signals. The AEQ block resides within the PMA of the receiver channel and is available on all GX channels.

Note: AEQ is supported by Arria V GZ devices, but not Arria V GX, GT, SX, and ST devices.

There are two AEQ modes: one-time and powerdown:

  • One-time mode—The AEQ finds a stable setting of the receiver equalizer and locks to that value. After the stable setting is locked, the equalizer values do not.
  • Powerdown mode—The AEQ of the specific channel is placed in standby mode and the CTLE uses the manually set value. Note that the CTLE cannot be bypassed.

You can dynamically switch between these modes.