Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

4.2.1. Gigabit Ethernet Transceiver Datapath

Figure 108. Transceiver Datapath in GbE-1.25 Gbps Configuration

Figure 109. Transceiver Datapath in GbE-3.125 Gbps Configuration

Table 59.  Transceiver Datapath Clock Frequencies in GbE Configuration
Functional Mode Data Rate High-Speed Serial Clock Frequency Parallel Recovered Clock and Low-Speed Parallel Clock Frequency FPGA Fabric-Transceiver Interface Clock Frequency
GbE-1.25 Gbps 1.25 Gbps 625 MHz 125 MHz 125 MHz
GbE-3.125 Gbps 3.125 Gbps 1562.5 MHz 312.5 MHz 156.25 MHz

8B/10B Encoder

In GbE configuration, the 8B/10B encoder clocks in 8-bit data and 1-bit control identifiers from the transmitter phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded data is fed to the serializer.

For more information about the 8B/10B encoder functionality, refer to the Transceiver Architecture for Arria V Devices chapter.

Rate Match FIFO

In GbE configuration, the rate match FIFO is capable of compensating for up to ±100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. The GbE protocol requires that the transmitter send idle ordered sets /I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during interpacket gaps, adhering to the rules listed in the IEEE 802.3 specification.

The rate match operation begins after the synchronization state machine in the word aligner indicates that the synchronization is acquired-by driving the rx_syncstatus signal high. The rate matcher always deletes or inserts both symbols (/K28.5/ and /D16.2/) of the /I2/ ordered sets, even if only one symbol needs to be deleted to prevent the rate match FIFO from overflowing or underrunning. The rate matcher can insert or delete as many /I2/ ordered sets as necessary to perform the rate match operation.

Two flags are forwarded to the FPGA fabric:

  • rx_rmfifodatadeleted—Asserted for two clock cycles for each deleted /I2/ ordered set to indicate the rate match FIFO deletion event
  • rx_rmfifodatainserted—Asserted for two clock cycles for each inserted /I2/ ordered set to indicate the rate match FIFO insertion event
Note: If you have the autonegotiation state machine in the FPGA, note that the rate match FIFO is capable of inserting or deleting the first two bytes (/K28.5//D2.2/) of /C2/ ordered sets during autonegotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered sets can cause the autonegotiation link to fail. For more information, refer to the Altera Knowledge Base Support Solution.

For more information about the rate match FIFO, refer to the Transceiver Architecture for Arria V Devices chapter.

GbE Protocol-Ordered Sets and Special Code Groups

Table 60.  GIGE Ordered SetsThe following ordered sets and special code groups are specified in the IEEE 802.3-2008 specification.
Code Ordered Set Number of Code Groups Encoding



Alternating /C1/ and /C2/


Configuration 1


/K28.5/D21.5/ Config_Reg 35


Configuration 2


/K28.5/D2.2/ Config_Reg 35



Correcting /I1/, Preserving /I2/



























Table 61.  Synchronization State Machine Parameters in GbE Mode
Synchronization State Machine Parameters Setting
Number of valid {/K28.5/, /Dx,y/} ordered sets received to achieve synchronization 3
Number of errors received to lose synchronization 4
Number of continuous good code groups received to reduce the error count by 1 4
Figure 110. Synchronization State Machine in GbE ModeThis figure is from “Figure 36–9” in the IEEE 802.3-2008 specification. For more details about the 1000BASE-X implementation, refer to Clause 36 of the IEEE 802.3-2008 specification.

35 Two data code groups represent the Config_Reg value.