Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Serializer

The serializer provides parallel-to-serial data conversion and sends the data LSB first from the transmitter physical coding sublayer (PCS) to the transmitter buffer. Additionally, the serializer provides the polarity inversion and bit reversal features.

Polarity Inversion

The positive and negative signals of a serial differential link might accidentally be swapped during board layout.

The polarity inversion feature of the transmitter corrects this error without requiring a board respin or major updates to the logic in the FPGA fabric. The polarity inversion feature inverts the polarity of every bit at the input to the serializer, which has the same effect as swapping the positive and negative signals of the serial differential link.

Polarity inversion is controlled dynamically with the tx_invpolarity register. When you enable the polarity inversion feature, it may cause initial disparity errors at the receiver with 8B/10B-coded data. The downstream system at the receiver must be able to tolerate these disparity errors.

Enabling polarity inversion midway through a serialized word corrupts the word.

Bit Reversal

You can reverse the transmission bit order to achieve MSB-to-LSB ordering using the bit reversal feature at the transmitter.
Table 9.  Bit Reversal Feature
Transmission Bit Order
Bit Reversal Option 8- or 10-bit Serialization Factor 16- or 20-bit Serialization Factor
Disabled (default) LSB to MSB LSB to MSB
Enabled MSB to LSB

For example:

8-bit—D[7:0] rewired to D[0:7]

10-bit—D[9:0] rewired to D[0:9]


For example:

16-bit—D[15:0] rewired to D[0:15]

20-bit—D[19:0] rewired to D[0:19]