Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Disparity Checker

The design of the disparity checker is based on the Interlaken protocol specifications. After word synchronization is achieved, the disparity checker monitors the status of the 67th bit of the incoming word and determines whether or not to invert bits [63:0] of the received word.
Note: The disparity checker is only used in Interlaken configurations.
Table 35.  Interpretation of the MSB in the 67-Bit Payload for Arria V Devices
MSB Interpretation
0 Bits [63:0] are not inverted; the disparity checker processes the word without modification
1 Bits [63:0] are inverted; the disparity checker inverts the word to achieve the original word before processing it