Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

1.2.4. PCIe Gen3 PCS Architecture

Arria V supports the PCIe Gen3 Base specification. The PCIe Gen3 uses a 128/130 bit block encoding/decoding scheme which is different from the 8B/10B scheme used in Gen1 and Gen2. The 130-bit block contains a 2-bit sync header and 128-bit data payload. For this reason, the PCIe Gen3 PCS has a separate data path as compared to the PCIe Gen1 or Gen2 PCS. The PCIe Gen3 PCS supports the PHY Interface for the PCI Express (PIPE) interface with the hard IP enabled and with the hard IP bypassed.

This PIPE interface supports the seamless switching of Data and Clock between the Gen1, Gen2, and Gen3 PCS, and provides support for PIPE 3.0 features.

The overall simplified PCIe Gen3 PCS the following architecture diagram. Note that the RX/TX Phase Comp FIFOs are physically placed in, and shared with the standard 8GB PCS.

Figure 38. PCIe Gen3 PCS Top Level Block Diagram