Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Word Aligner

The Word Aligner provides word boundary restoration during link synchronization.

Parallel data at the input of the receiver PCS loses the word boundary of the upstream transmitter from the serial-to-parallel conversion in the deserializer. The word aligner provides word boundary restoration during link synchronization with the following four modes:

  • Manual alignment mode
  • Bit-slip mode
  • Automatic synchronization state machine mode
  • Deterministic latency state machine mode

The word aligner searches for a predefined alignment pattern in the deserialized data to identify the correct boundary and restores the word boundary during link synchronization. The alignment pattern is predefined for standard serial protocols according to the respective protocol specifications to achieve synchronization or you can specify the settings with a custom word alignment pattern for proprietary protocol implementations. Except for bit-slip mode, after completing word alignment, the deserialized data is synchronized to have the word alignment pattern at the LSB portion of the aligned data.

In addition to restoring the word boundary, the word aligner also supports optional features.

Table 22.  Optional Word Aligner Features
Feature Availability
Programmable Run-Length Violation Detection All transceiver configurations
Receiver Polarity Inversion All transceiver configurations except PCIe
Receiver Bit Reversal Custom single- and double-width configurations only
Receiver Byte Reversal Custom double-width configuration only

The operation mode and alignment pattern length support varies depending on the word aligner configurations.

Table 23.  Word Aligner Operation Mode and Pattern Length Support
PCS Mode PMA–PCS Interface Width Word Aligner Mode Alignment Pattern Length
Single Width 8 bits Manual alignment 8 bits or 16 bits
10 bits Manual alignment 7 or 10 bits
Automatic synchronization state machine 7 or 10 bits 6
Deterministic latency state machine 10 bits 7
Double Width 16 bits Manual alignment 8, 16, or 32 bits
20 bits Manual alignment 7, 10, 20, or 40 bits
Deterministic latency state machine 10 bits 7

When the 8B/10B encoder/decoder is enabled, the word aligner detects both positive and negative disparities of the alignment pattern. For example, if you specify a /K28.5/ (b’0011111010) pattern as the comma, rx_patterndetect is asserted if b’0011111010 or b’1100000101 is detected in the incoming data.

6 For PCIe implementation, the word aligner is configured using the automatic synchronization state machine with alignment pattern length of 10 bits.
7 For more information about CPRI in deterministic latency state machine, refer to the CPRI Enhancements section of the Transceiver Protocol Configurations in Arria V Devices chapter.