Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

1.1.3. Transceiver Channel Architecture

The Arria V transceivers are comprised of a transmitter and receiver that can operate individually or simultaneously—providing a full-duplex physical layer implementation for high-speed serial interfacing. Each transmitter and receiver are divided into two blocks: PMA and PCS. The PMA block connects the FPGA to the channel, generates the required clocks, and converts the data from parallel to serial or serial to parallel. The PCS block performs digital processing logic between the PMA and the FPGA core.

Multiply the interface speed together with the serialization factor to determine the maximum supported data rate for any given transceiver configuration. For example, the Arria V GT supports a maximum interface speed of 161 MHz in PMA direct mode. To calculate the maximum supported data rate for a serialization factor of 20 in PMA direct mode, multiply 161 x 20 = 3220 Mbps.

Figure 8. Full Duplex Channel Interface Architecture
Table 7.  Architecture Differences Between 6- and 10-Gbps Arria V GT/ST Channels and Arria V GZ Channels
Architecture Differences 6-Gbps Channel 10-Gbps Channel2 Arria V GZ Channel
Transmitter PCS Capability Up to 6.5536 Gbps Up to 6.5536 Gbps Up to 12.5 Gbps
Receiver PCS Capability Up to 6.5536 Gbps Up to 6.5536 Gbps 3 Up to 12.5 Gbps
Transmitter/Receiver PMA Capability Up to 6.5536 Gbps Up to 10.3125 Gbps Up to 12.5 Gbps
PMA Direct (PMA-Fabric Interface) Not supported Supported Supported
Serialization Factor 8, 10, 16, 20 8, 10, 16, 20, 64, 80 8, 10, 16, 20, 32, 40, 64, 80
2 10-Gbps channel is only available in GT and ST variants.
3 Arria V GT/ST devices cannot use the PCS when running at 10 Gbps.