Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

2.3.3. Receiver Datapath Interface Clock

The 6-Gbps receiver datapath interface is comprised of the read side RX phase compensation FIFO.

The read side of the RX phase compensation FIFO makes up the 6-Gbps receiver datapath interface. The receiver datapath interface clock clocks this interface. The receiver PCS forwards the following clocks to the FPGA fabric:

  • rx_clkout—for each receiver channel in a non-bonded configuration when you do not use a rate matcher
  • tx_clkout—for each receiver channel in a non-bonded configuration when you use a rate matcher
  • single rx_clkout[0]—for all receiver channels in a bonded configuration
Figure 76. 6-Gbps Receiver Datapath Interface Clocking

All configurations that use the PCS channel must have a 0 ppm difference between the receiver datapath interface clock and the read side clock of the RX phase compensation FIFO.

For the 10-Gbps transceivers in Arria V GT/ST devices, there are no PCS blocks. The only receiver datapath available is a direct connection from the receiver PMA deserializer to the FPGA fabric.

For each receiver channel in a non-bonded configuration, the receiver PMA forwards the rx_clkout clock to the FPGA fabric.

Figure 77.  Arria V GT/ST 10-Gbps Receiver Datapath Interface Clocking

Note: For more information about interface clocking for each configuration, refer to the Transceiver Custom Configuration in Arria V Devices and Transceiver Protocol Configurations in Arria V Devices chapters.

You can clock the receiver datapath interface by one of the following options:

  • The Quartus II-selected receiver datapath interface clock
  • The user-selected receiver datapath interface clock
Note: To reduce GCLK, RCLK, and PCLK resource utilization in your design, you can select the user-selection option to share the transceiver datapath interface clocks.