Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Transmitter Buffer

The transmitter buffer includes additional circuitry to improve signal integrity, such as the programmable differential output voltage (VOD), programmable three-tap pre-emphasis circuitry, internal termination circuitry, and PCIe receiver detect capability to support a PCIe configuration.

Modifying programmable values within transmitter output buffers can be performed by a single reconfiguration controller for the entire FPGA, or multiple reconfiguration controllers if desired. Within each transceiver bank a maximum of two reconfiguration controllers is allowed; one for the three-transceiver triplet in the upper-half of the bank, and one for the lower-half. This is due to a single slave interface to all PLLs and PMAs within each triplet. Therefore, many triplets can be connected to a single reconfiguration controller, but only one reconfiguration controller can be connected to the three transceivers within any triplet.

Note: A maximum of one reconfiguration controller is allowed per transceiver bank upper-half or lower-half triplet.
Note: The Arria V GT transmitter buffer has only one tap for the pre-emphasis.
Figure 10. Transmitter Buffer in Arria V Devices

Table 10.  Description of the Transmitter Buffer Features
Category Features Description
Improve Signal Integrity Programmable Differential Output Voltage (VOD) Controls the current mode drivers for signal amplitude to handle different trace lengths, various backplanes, and receiver requirements. The actual VOD level is a function of the current setting and the transmitter termination value.
Programmable Pre-Emphasis

Boosts the high-frequency components of the transmitted signal, which may be attenuated when propagating through the transmission medium. The physical transmission medium can be represented as a low-pass filter in the frequency domain. Variation in the signal frequency response that is caused by attenuation significantly increases the data-dependent jitter and other intersymbol interference (ISI) effects at the receiver end. Using the pre-emphasis feature maximizes the data opening at the far-end receiver.

Arria V GZ channels provide three pre-emphasis taps: pre-tap (16 settings), first post-tap (32 settings), and second post-tap (16 settings). Arria V GX, SX, GT and ST provides only one pre-emphasis tap which is first post-tap (32 settings).The pre-tap sets the pre-emphasis on the data bit before the transition. The first post-tap and second post-tap set the pre-emphasis on the transition bit and the following bit, respectively. The pre-tap and second post-tap also provide inversion control, shown by negative values.

Programmable Slew Rate Controls the rate of change for the signal transition.
Save Board Space and Cost On-Chip Biasing Establishes the required transmitter common-mode voltage (TX VCM) level at the transmitter output. The circuitry is available only if you enable on-chip termination (OCT). When you disable OCT, you must implement off-chip biasing circuitry to establish the required TX VCM level.
Differential OCT The termination resistance is adjusted by the calibration circuitry, which compensates for the process, voltage, and temperature variations (PVT). You can disable OCT and use external termination. However, you must implement off-chip biasing circuitry to establish the required TX VCM level. TX VCM is tri-stated when using external termination.
Reduce Power Programmable VCM Current Strength Controls the impedance of VCM. A higher impedance setting reduces current consumption from the on-chip biasing circuitry.
Protocol-Specific Function Transmitter Output Tri-State

Enables the transmitter differential pair voltages to be held constant at the same value determined by the TX VCM level with the transmitter in the high impedance state.

The transmitter output tri-state feature is compliant with differential and common-mode voltage levels and operation time requirements for transmitter electrical idle, as specified in the PCI Express Base Specification 2.0 for Gen1 and Gen2 signaling rates, and PCI Express Base Specification 3.0 for Gen3 signaling rates (Arria V GZ only).

Receiver Detect

Provides link partner detection capability at the transmitter end using an analog mechanism for the receiver detection sequence during link initialization in the Detect state of the PCI Express® (PCIe) Link Training and Status State Machine (LTSSM) states. The circuit detects if there is a receiver downstream by changing the transmitter VCM to create a step voltage and measuring the resulting voltage rise time.

For proper functionality, the series capacitor (AC-coupled link) and receiver termination values must comply with the PCI Express Base Specification 2.0 for Gen1 and Gen2 signaling rates and PCI Express Base Specification 3.0 for Gen3 signaling rates (Arria V GZ only). The circuit is clocked using fixedclk and requires that the transmitter OCT be enabled with the output tri-stated.

Figure 11. Example of Pre-Emphasis Effect on Signal Transmission at Transmitter OutputShows the signal transmission at the transmitter output with and without applying pre-emphasis post-tap for a 5 Gigabit per second (Gbps) signal with an alternating data pattern of five 1s and five 0s.

The receiver can be AC- or DC-coupled to a transmitter. In an AC-coupled link, the AC-coupling capacitor blocks the transmitter VCM. At the receiver end, the termination and biasing circuitry restores the VCM level that is required by the receiver.

Figure 12. AC-Coupled Link with Arria V Transmitter

When used in a DC-coupled link, the transmitter Vcm is fixed to 0.7 V. The receiver Vcm is required to be at 0.7 V. DC coupling is supported for serial data rates up to 3.2 Gbps.

You can DC-couple the Arria V GZ channel transmitter only to another Arria V GZ channel receiver for the entire datarate range from 600 Mbps to 12.5 Gbps so long as the same VCM value is observed.

Figure 13. DC-Coupled Link with Arria V Transmitter