Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Transmitter Phase Compensation FIFO

The transmitter phase compensation FIFO is four words deep and interfaces the control and data signals between the transmitter PCS and FPGA fabric or PCIe hard IP block.

The FIFO supports the following operations:

  • Phase compensation mode with various clocking modes on the read clock and write clock
  • Registered mode with only one clock cycle of datapath latency