Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Word Aligner in Deterministic Latency State Machine Mode

In deterministic latency state machine mode, word alignment is achieved by performing a clock-slip in the deserializer until the deserialized data coming into the receiver PCS is word-aligned.

The state machine controls the clock-slip process in the deserializer after the word aligner has found the alignment pattern and identified the word boundary. Deterministic latency state machine mode offers a reduced latency uncertainty in the word alignment operation for applications that require deterministic latency.

After rx_syncstatus is asserted and if the incoming data is corrupted causing an invalid code group, rx_syncstatus remains asserted. The rx_errdetect register will be set to 1 (indicating RX 8B/10B error detected). When this happens, the manual alignment mode is not be able to de-assert the rx_syncstatus signal. You must manually assert rx_digitalreset or manually control rx_std_wa_patternalign to resynchronize a new word boundary search whenever rx_errdetect shows an error.

PCS Mode PMA–PCS Interface Width Word Alignment Operation
Single Width 10 bits
  1. After rx_digitalreset deasserts, the word aligner starts looking for the predefined word alignment pattern, or its complement, in the received data stream and automatically aligns to the new word boundary.
  2. After the pattern is found and the word boundary is identified, the state machine controls the clock-slip process in the deserializer.
  3. When the clock-slip is complete, the deserialized data coming into the receiver PCS is word-aligned and is indicated by the value 1 in the rx_syncstatus register until rx_digitalreset is deasserted.
  4. To resynchronize to the new word boundary, the Avalon-MM register rx_enapatternalign (not available as a signal) must be reasserted to initiate another pattern alignment. Asserting rx_enapatternalign may cause the extra shifting in the RX datapath if rx_enablepatternalign is asserted while bit slipping is in progress. Consequently, rx_enapatternalign should only be asserted under the following conditions:
    • rx_syncstatus is asserted
    • rx_bitslipboundaryselectout changes from a non-zero value to zero or 1
  5. When the word aligner synchronizes to the new word boundary, rx_syncstatus has a value of 1 until rx_digitalreset is deasserted or rx_enapatternalign is set to 1. rx_patterndetect has a value of 1 whenever a word alignment pattern is found for one parallel clock cycle regardless of whether or not the word aligner is triggered to align to the new word boundary.
Double Width 20 bits