1. Transceiver Architecture in Arria V Devices
2. Transceiver Clocking in Arria V Devices
3. Transceiver Reset Control in Arria V Devices
4. Transceiver Protocol Configurations in Arria V Devices
5. Transceiver Custom Configurations in Arria V Devices
6. Transceiver Configurations in Arria V GZ Devices
7. Transceiver Loopback Support in Arria V Devices
8. Dynamic Reconfiguration in Arria V Devices
1.2.2.1.1. Word Aligner in Manual Alignment Mode
1.2.2.1.2. Bit-Slip Mode
1.2.2.1.3. Word Aligner in Automatic Synchronization State Machine Mode
1.2.2.1.4. Word Aligner in Deterministic Latency State Machine Mode
1.2.2.1.5. Programmable Run-Length Violation Detection
1.2.2.1.6. Receiver Polarity Inversion
1.2.2.1.7. Bit Reversal
1.2.2.1.8. Receiver Byte Reversal
3.1. PHY IP Embedded Reset Controller
3.2. User-Coded Reset Controller
3.3. Transceiver Reset Using Avalon Memory Map Registers
3.4. Clock Data Recovery in Manual Lock Mode
Resetting the Transceiver During Dynamic Reconfiguration
3.6. Transceiver Blocks Affected by the Reset and Powerdown Signals
3.7. Transceiver Power-Down
3.8. Document Revision History
3.2.1. User-Coded Reset Controller Signals
3.2.2. Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up
3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation
3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration
3.2.5. Resetting the Receiver with the User-Coded Reset Controller During Device Operation
4.1. PCI Express
4.2. Gigabit Ethernet
4.3. XAUI
4.4. 10GBASE-R
4.5. Serial Digital Interface
4.6. Gigabit-Capable Passive Optical Network (GPON)
4.7. Serial Data Converter (SDC) JESD204
4.8. SATA and SAS Protocols
4.9. Deterministic Latency Protocols—CPRI and OBSAI
4.10. Serial RapidIO
4.11. Document Revision History
4.1.2.1. PIPE Interface
4.1.2.2. Transmitter Electrical Idle Generation
4.1.2.3. Power State Management
4.1.2.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support
4.1.2.5. Receiver Status
4.1.2.6. Receiver Detection
4.1.2.7. Clock Rate Compensation Up to ±300 ppm
4.1.2.8. PCIe Reverse Parallel Loopback
6.1.1. 10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration
6.1.2. 10GBASE-R and 10GBASE-KR Supported Features
6.1.3. 1000BASE-X and 1000BASE-KX Transceiver Datapath
6.1.4. 1000BASE-X and 1000BASE-KX Supported Features
6.1.5. Synchronization State Machine Parameters in 1000BASE-X and 1000BASE-KX Configurations
6.1.6. Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX Configurations
6.3.1. Transceiver Datapath Configuration
6.3.2. Supported Features for PCIe Configurations
6.3.3. Supported Features for PCIe Gen3
6.3.4. Transceiver Clocking and Channel Placement Guidelines
6.3.5. Advanced Channel Placement Guidelines for PIPE Configurations
6.3.6. Transceiver Clocking for PCIe Gen3
6.7.1. Protocols and Transceiver PHY IP Support
6.7.2. Native PHY Transceiver Datapath Configuration
6.7.3. Standard PCS Features
6.7.4. 10G PCS Supported Features
6.7.5. 10G Datapath Configurations with Native PHY IP
6.7.6. PMA Direct Supported Features
6.7.7. Channel and PCS Datapath Dynamic Switching Reconfiguration
8.1. Dynamic Reconfiguration Features
8.2. Offset Cancellation
8.3. Transmitter Duty Cycle Distortion Calibration
8.4. PMA Analog Controls Reconfiguration
8.5. Dynamic Reconfiguration of Loopback Modes
8.6. Transceiver PLL Reconfiguration
8.7. Transceiver Channel Reconfiguration
8.8. Transceiver Interface Reconfiguration
8.9. Reduced .mif Reconfiguration
8.10. On-Chip Signal Quality Monitoring (Eye Viewer)
8.11. Adaptive Equalization
8.12. Decision Feedback Equalization
8.13. Unsupported Reconfiguration Modes
8.14. Document Revision History
6.7.5. 10G Datapath Configurations with Native PHY IP
Transceiver PHY IP | Native PHY IP | |||||
---|---|---|---|---|---|---|
Link | 10/40GBASE-R/KR | 10/40GBASE-R with 1588 | Interlaken | SFI-5.2 | 10G SDI | Other 10G Protocols (Basic Mode) |
Lane Datarate | 10.3125Gbps | 10.3125Gbps | 3.125 - 12.5Gbps | 0.6 - 12.5Gbps 44 | 10.692Gbps | 0.6 - 12.5Gbps 44 |
PMA Channel Bonding Option45 46 | Non-bonded, xN,feedback compensation | Non-bonded, xN, feedback compensation | Non-bonded | Non-bonded, xN, feedback compensation | Non-bonded, xN, feedback compensation | Non-bonded, xN, feedback compensation |
PCS Datapath | 10G PCS | 10G PCS | 10G PCS | 10G PCS | 10G PCS | 10G PCS |
PCS-PMA Interface Width (Serialization Factor) | 40-bit | 40-bit | 40-bit | 32/40/64-bit | 40-bit | 32/40/64-bit |
Gearbox Ratios | 66:40 47 | 66:40 47 | 67:40 | 32:32, 64:3247, 40:40, 64:64 | 50:40 47 | 32:32, 64:3247, 40:40, 66:4047, 64:64 |
Block Synchronizer | Enabled | Enabled | Enabled | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) |
Disparity Generator, Checker | Bypassed | Bypassed | Enabled | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) |
Scrambler, Descrambler | Enabled | Enabled | Enabled | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) |
64B/66B Encoder, Decoder | Enabled | Enabled | Bypassed | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) |
BER Monitor | Enabled | Enabled | Bypassed | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) |
CRC32 Generator, Checker | Bypassed | Bypassed | Enabled | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) |
Frame Generator, Synchronizer | Bypassed | Bypassed | Enabled | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) | Bypassed (Low Latency Mode) |
RX FIFO (Mode) | Clock Compensation Mode | Registered Mode | Interlaken Mode | Phase Compensation Mode | Phase Compensation Mode | Phase Compensation Mode (Low Latency Mode) |
TX FIFO (Mode) | Phase Compensation Mode | Registered Mode | Interlaken Mode | Phase Compensation Mode | Phase Compensation Mode | Phase Compensation Mode (Low Latency Mode) |
TX/RX 10G PCS Latency (Parallel Clock Cycles) 48 | TX: 8-12 RX: 15-34 |
TX: 1-4 RX: 2-5 |
TX: 7-28 RX: 14-21 |
TX: 6-10 (64:32) TX: 7-10 (64:64, 40:40, 32:32) RX: 6-10 (64:32) RX: 7-10 (64:64, 40:40, 32:32) |
TX: 7-11 RX: 6-12 |
TX: 6-10 (64:32) TX: 6-11 (66:40) TX: 7-10 (64:64, 40:40, 32:32) RX: 6-10 (64:32) RX: 6-11 (66:40) RX: 7-10 (64:64, 40:40, 32:32) |
FPGA Fabric-to- Transceiver Interface Widths | 66-bit | 66-bit | 67-bit | 32-bit 40-bit 64-bit |
50-bit | 32-bit 40-bit 64-bit 66-bit |
FPGA Fabric-to- Transceiver Interface Width Maximum Frequencies | 66-bit: 156.25 MHz | 66-bit: 156.25 MHz | 67-bit: 78.125-312.5 MHz 49 | 32-bit (32:32): 340.0 MHz 40-bit (40:40): 312.5 MHz 64-bit (64:32): 170.0 MHz 5064-bit (64:64): 195.4 MHz |
50-bit: 213.8 MHz 49 | 32-bit (32:32): 340.0 MHz 40-bit (40:40): 312.5 MHz 64-bit (64:32): 170.0 MHz 5064-bit (64:64): 195.4 MHz 66-bit (66:40): 189.4 MHz 49 |
44 Gearbox ratios of 64:32 and 32:32 have a maximum supported datarate of 10.88Gbps.
45 For xN bonding, the number of bonded channels is up to four using CMU PLL and up to six using ATX PLL, provided the data rate is supported by the CMU PLL and ATX PLL.
46 Bonding more than six channels requires PLL feedback compensation bonding. PLL feedback compensation bonding requires one PLL per transceiver bank and the PLL reference clock frequency must have the same value as the lane data rate divided by the serialization factor.
47 May require the use of an internal fractional PLL (fPLL) for selected Gearbox ratio.
48 PCS Latency values are with default recommended FIFO partially full and partially empty values. Disabled if Standard PCS 8B/10 Encoder/Decoder is used.
49 PCS tx_clkout frequency output is lane datarate/40 for 10G-SDI, Interlaken, and Basic Mode.
50 PCS tx_clkout frequency output is lane datarate/32 for SFI-S and Basic Mode.