Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

2.2. Internal Clocking

In the internal clocking architecture, different physical coding sublayer (PCS) configurations and channel bonding options result in various transceiver clock paths.
Table 39.  Internal Clocking SubsectionsThe labels listed in the following table and shown in the figure following mark the three sections of the transceiver internal clocking.
Label Scope Description
A Transmitter Clock Network Clock distribution from transmitter PLLs to channels
B Transmitter Clocking Clocking architecture within transmitter channel datapath
C Receiver Clocking Clocking architecture within receiver channel datapath
Figure 47. Internal Clocking

Note: For Arria V GZ devices, the x6 clock lines can support data rates up to 12.5 Gbps and the xN clock lines can support data rates up to 9.8304 Gbps.