Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

6.6.1. Standard PCS Configurations—Custom Datapath

Use the Custom PHY IP to enable the standard PCS in custom datapath. To implement a Custom PHY link, instantiate the Custom PHY IP in the IP Catalog, under Transceiver PHY in the Interfaces menu. Define your custom datapath configurations by selecting the blocks to use and the appropriate data width.

The custom datapath consists of the following blocks:

  • 8B/10B encoder and decoder
  • Word aligner
  • Deskew FIFO
  • Rate match FIFO (clock rate compensation FIFO)
  • Byte ordering block
  • Phase compensation FIFO
  • Byte serializer and deserializer
  • Transmit bit slip
Figure 203. Standard PCS Custom Datapath and Clocking

You can divide the custom datapath into two configurations based on the FPGA fabric-transceiver interface width and the PMA-PCS interface width (serialization factor):

  • Custom 8/10-bit-width—the PCS-PMA interface width is in 8-bit or 10-bit mode for lower data rates.
  • Custom 16/20-bit-width—the PCS-PMA interface width is in 16-bit or 20-bit mode for higher data rates.
Table 83.  PCS-PMA Interface Widths and Supported Data Rates
PCS-PMA Interface Width Supported Data Rate Range PMA
Custom 8-bit width 600 Mbps to 4.24 Gbps
Custom 10-bit width 600 Mbps to 5.30 Gbps
Custom 16-bit width 600 Mbps to 7.84 Gbps
Custom 20-bit width 600 Mbps to 9.80 Gbps
Figure 204. Standard PCS Custom 8-Bit PMA-PCS Interface Width

Figure 205. Standard PCS Custom 10-Bit PMA-PCS Interface Width

Figure 206. Standard PCS Custom 16-Bit PMA-PCS Interface Width

Figure 207. Standard PCS Custom 20-Bit PMA-PCS Interface Width