Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

4.1.1. PCIe Transceiver Datapath

Figure 92. PCIe Gen1 and Gen2 PIPE Datapath Configuration
Figure 93. PCIe Gen1 and Gen2 Hard IP and PHY IP Core for PCI Express Datapath Configuration

The transceiver datapath clocking varies between non-bonded (x1) and bonded (x2, x4, and x8) configurations.

Transceiver Channel Datapath

Figure 94. Transceiver Channel Datapath in a PIPE Configuration