Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

2.3.1. Transceiver Datapath Interface Clocking

There are two types of design considerations for clock optimization when interfacing the transceiver datapath to the FPGA fabric:
  • PCS with FIFO in phase compensation mode – share clock network for identical channels
  • PCS with FIFO in registered mode or PMA direct mode – refer to AN580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode for additional timing closure techniques between transceiver and FPGA fabric
Note: For Arria V (GX, GT, ST and SX) devices, the PMA clock for channel 1 and channel 2 of GXB_L0 and GXB_R0 cannot be routed out of the FPGA fabric.