Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

4.3.1. Transceiver Datapath in a XAUI Configuration

The XAUI PCS is implemented in soft logic inside the FPGA core when using the XAUI PHY IP core. You must ensure that your channel placement is compatible with the soft PCS implementation.
Figure 112. XAUI Configuration Datapath

Figure 113. Transceiver Channel Datapath for XAUI ConfigurationStandard PCS in a low latency configuration is used in this configuration. Additionally, a portion of the PCS is implemented in soft logic.