Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Disparity Generator

The disparity generator block conforms to the Interlaken protocol specification and provides a DC-balanced data output. The disparity generator receives data from the scrambler and inverts the running disparity to stay within the ±96-bit boundary. To ensure this running disparity requirement, the disparity generator inverts bits [63:0] and sets bit [66] to indicate the inversion.
Note: The disparity generator is used only in Interlaken configurations.
Table 34.  Interpretation of the MSB in the 67-Bit Payload for Arria V Devices
MSB Interpretation
0 Bits [63:0] are not inverted; the disparity generator processes the word without modification
1 Bits [63:0] are inverted; the disparity generator inverts the word before processing it