Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Byte Ordering in Single-Width Mode

Byte ordering is supported only when you enable the byte deserializer.

Table 32.  Byte Ordering Operation in Single-Width Mode
PMA–PCS Interface Width FPGA Fabric–Transceiver Interface Width 8B/10B Decoder Byte Ordering Pattern Length Pad Pattern Length
8 bits 16 bits Disabled 8 bits 8 bits
10 bits 16 bits Enabled 9 bits8 9 bits 8
20 bits Disabled 10 bits 10 bits
Figure 32. Byte Ordering Operation Example in Single-Width ModeAn example of a byte ordering operation in single-width mode (8-bit PMA-PCS interface width) where A is the predefined byte ordering pattern and P is the predefined pad pattern.

8 The MSB of the 9-bit pattern represents the 1-bit control identifier of the 8B/10B-decoded data. The lower 8 bits represent the 8-bit decoded code.