Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Receiver PMA Datapath

Describes the receiver buffer, channel phase-locked loop (PLL) configured for clock data recovery (CDR) operation, and deserializer blocks in the receiver PMA datapath.
Table 11.  Functional Blocks in the Receiver PMA Datapath
Block Functionality
Receiver Buffer
  • Receives the serial data stream and feeds the stream to the channel PLL if you configure the channel PLL as a CDR.
  • Supports the following features:
    • Programmable CTLE (Continuous Time Linear Equalization)
    • Programmable DC gain
    • Programmable VCM current strength
    • On-chip biasing for common-mode voltage (RX VCM )
    • I/O standard (1.4 V (Arria V GZ), PCML, 1.5 V PCML, 2.5 V PCML, LVDS, LVPECL )
    • Differential OCT (85, 100, 120 and 150 Ω )
    • Signal detect
Channel PLL
  • Recovers the clock and serial data stream if you configure the channel PLL as a CDR.
  • Requires offset cancellation to correct the analog offset voltages.
  • If you do not use the channel PLL as a CDR, you can configure the channel PLL as a CMU PLL for clocking the transceivers. For more information about the channel PLL configured as a CMU PLL, refer to CMU PLL.
  • Converts the incoming high-speed serial data from the receiver buffer to low-speed parallel data for the receiver PCS.
  • Receives serial data in LSB-to-MSB order.
  • Supports the optional clock-slip feature for applications with stringent latency uncertainty requirement.
  • Supports 8, 10, 16, and 20-bit deserialization factors in Arria V GX, SX, GT, ST, and GZ devices.
  • Additionally supports the 64 and 80-bit serialization factor for 10-Gbps transceiver channels Arria V ST and GT devices.
  • Additionally supports the 32, 40, 64, and 80-bit serialization factor in Arria V GZ devices.