Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

2.1.1. Reference Clock Network

The dedicated refclk pin can provide the reference clock to multiple channel PLLs, fractional PLLs or an ATX PLL (for Arria V GZ devices).

Designs that use multiple transmitter PLL and CDRs with the same input reference clock frequency can share the same dedicated refclk pin. Each dedicated refclk pin can drive any transmitter PLL or CDR on the same side of device through the reference clock network.