Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents Auxiliary Transmit (ATX) PLL Architecture

Arria V GZ devices contain two ATX PLLs per transceiver bank that can generate the high-speed clocks for the transmitter channels.

Compared with CMU PLLs, ATX PLLs have lower jitter and do not consume a transceiver channel; however an ATX PLL’s frequency range is more limited.

The serial clock from the ATX PLL is routed to the transmitter clock dividers and can be further divided down to half the data rate of the individual channels. For best performance you should use the reference clock input that resides in the same transceiver block as your channel. However, you can use any dedicated reference clocks along the same side of the device to clock the ATX PLL.

Note: Altera recommends that all Arria V GZ devices use the ATX PLL for channels operating between 8 to 12.5 Gbps data rates and to use the dedicated reference clock input residing in the same transceiver bank for the selected ATX PLL for best performance
Figure 19. ATX PLL Architecture