Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

1.2.1. Transmitter PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ Standard PCS

This section describes the transmitter phase compensation FIFO, byte serializer, 8B/10B encoder, and transmitter bit-slip blocks in the transmitter PCS datapaths.
Table 17.  Functional Blocks in the Transmitter PCS Datapath
Block Functionality
Transmitter Phase Compensation FIFO
  • Compensates for the phase difference between the low-speed parallel clock and the FPGA fabric interface clock when interfacing the transmitter PCS with the FPGA fabric directly or with the PCIe hard IP block
  • Supports operation in phase compensation and registered modes
Byte Serializer
  • Divides the FPGA fabric–transceiver interface frequency in half at the transmitter channel by doubling the transmitter input datapath width
  • Allows the transmitter channel to operate at higher data rates with the FPGA fabric–transceiver interface frequency that is within the maximum limit
  • Supports operation in double-width modes
8B/10B Encoder
  • Generates 10-bit code groups from 8-bit data and 1-bit control identifier, in compliance with Clause 36 of the IEEE 802.3 specification
  • Supports operation in single- and double-width modes, and running disparity control
Transmitter Bit-Slip
  • Enables user-controlled, bit-level delay in the data prior to serialization for serial transmission
  • Supports operation in single- and double-width modes