Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

1.2. PCS Architecture

The PCS architecture of Arria V GX/GT/SX/ST devices is slightly different from the GZ devices.

The GZ has three types of PCS blocks: standard PCS block, a 10G PCS block, and a PCIe Gen3 PCS block.

The GX, SX, GT, and ST devices have only one type of PCS block, which is similar to the GZ standard PCS block, except for the data rate support. The GX and GT PCS supports up to 6.5536 Gbps while the GZ PCS supports up to 9.8 Gbps. The 10G PCS of the GZ supports 12.5 Gbps, and the PCIe Gen3 PCS supports the PCIe Gen3 Base specification.

Figure 24. Transceiver Channel PCS in Arria V Devices
Note: For Arria V GT and ST devices, the PCS is not available when using the 10-Gbps channels; only the PMA is available. You must implement the PCS functions required for the interface using user logic in the FPGA fabric with an 80-bit FPGA fabric-transceiver width.

Arria V GZ transceiver PCS blocks fully support data rates up to 12.5 Gbps You have the option to bypass the PCS using the PMA direct mode.

Table 16.  PCS Datapath Configurations
Parameter Single-Width Double-Width
PMA–PCS Interface Width 8 or 10 bit 16 or 20 bit
FPGA Fabric–Transceiver Interface Width

8 or 10 bit

16 or 20 bit 5

16 or 20 bit

32 or 40 bit 5

Supported configurations PCIe Gen1, Gen2, and Gen3



Data rate range in a custom configuration 0.6 to 3.75 Gbps 1.0 to 11 Gbps
5 The byte serializer and deserializer are enabled.