Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Document Table of Contents

2.3. FPGA Fabric–Transceiver Interface Clocking

This section describes the clocking options available when the transceiver interfaces with the FPGA fabric.

The FPGA fabric–transceiver interface clocks can be subdivided into the following three categories:

  • Input reference clocks—Can be an FPGA fabric–transceiver interface clock. This may occur when the FPGA fabric-transceiver interface clock is forwarded to the FPGA fabric, where it can then clock logic.
    Note: The input reference clock can only be routed into the FPGA fabric if a transceiver is also instantiated.
  • Transceiver datapath interface clocks—Used to transfer data, control, and status signals between the FPGA fabric and the transceiver channels. The transceiver channel forwards the tx_clkout signal to the FPGA fabric to clock the data and control signals into the transmitter. The transceiver channel also forwards the recovered rx_clkout clock (in configurations without the rate matcher) or the tx_clkout clock (in configurations with the rate matcher) to the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric.
  • Other transceiver clocks—The following transceiver clocks form a part of the FPGA fabric–transceiver interface clocks:
    • phy_mgmt_clk—Avalon®-MM interface clock used for controlling the transceivers, dynamic reconfiguration, and calibration
    • fixed_clk—the 125 MHz fixed-rate clock used in the PCIe (PIPE) receiver detect circuitry
Table 47.  FPGA Fabric–Transceiver Interface Clocks
Clock Name Clock Description Interface Direction FPGA Fabric Clock Resource Utilization
tx_pll_refclk, rx_cdr_refclk Input reference clock used for clocking logic in the FPGA fabric Transceiver-to-FPGA fabric GCLK, RCLK, PCLK
tx_clkout, tx_pma_clkout Clock forwarded by the transceiver for clocking the transceiver datapath interface
rx_clkout, rx_pma_clkout Clock forwarded by the receiver for clocking the receiver datapath interface
tx_coreclkin User-selected clock for clocking the transmitter datapath interface FPGA fabric-to-transceiver
rx_coreclkin User-selected clock for clocking the receiver datapath interface
fixed_clk PCIe receiver detect clock
phy_mgmt_clk 30 Avalon-MM interface management clock
  • For Arria V GZ devices, you can forward the pll_refclk, tx_clkout, and rx_clkout clocks to a fractional PLL so that the fractional PLL can synthesize a clock for the FPGA logic. A second fractional PLL can be reached by periphery clocks, depending on your device and channel placement, and may require using a RGCLK or GCLK.
  • For more information about the GCLK, RCLK, and PCLK resources available in each device, refer to the Clock Networks and PLLs in Arria V Devices chapter
Table 48.  Configuration Specific Port Names for tx_clkout and rx_clkout
Configuration Port Name for tx_clkout Port Name for rx_clkout
Custom tx_clkout rx_clkout
Native - 10G PCS 31 tx_10g_clkout rx_10g_clkout
Native - Standard PCS tx_std_clkout rx_std_clkout
Native - PMA Direct tx_pma_clkout rx_pma_clkout
Interlaken 31 tx_clkout rx_clkout
Low Latency tx_clkout rx_clkout
PCIe pipe_pclk pipe_pclk
XAUI xgmii_tx_clk xgmii_rx_clk
30 The phy_mgmt_clk is a free-running clock that is not derived from the transceiver blocks.
31 Available for Arria V GZ devices only.