External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023

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Document Table of Contents

4.4.12. sideband0

address=43(32 bit)

Field Bit High Bit Low Description Access
mr_cmd_trigger 0 0 Mode Register Command Request. When asserted, indicates user request to execute mode register command. Controller clears bit to 0 when operation is completed. Register offset 37h and 38h must be properly configured before requesting Mode Register Command. Read offset 31h for Mode Register Command Status. Read/Write