External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023

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3.8.5. Using the Ping Pong PHY

The following steps describe how to use the Ping Pong PHY for Intel® Arria® 10 EMIF.
  1. Configure a single memory interface according to your requirements.
  2. Select Instantiate two controllers sharing a Ping Pong PHY on the General tab in the parameter editor.
    The Intel® Quartus® Prime software replicates the interface, resulting in two memory controllers and a shared PHY. The system configures the I/O bank-lane structure, without further input from you.

The location of the ALERT# pin is determined by settings in the Topology section of the Memory tab in the parameter editor.

If you set the the ALERT# pin placement parameter to I/O Lane with DQS Group, you can then specify the ALERT# location using the DQS Group of ALERT# parameter. The ALERT# pin will reside in the lane containing DQS[0] when you select a DQS Group of ALERT# value of 0, and in the lane containing DQS[1] when you select a DQS Group of ALERT# value of 1.