|Memory devices support
Supports the following memory devices:
- DDR4 SDRAM
- DDR3 SDRAM
- LPDDR3 for low power
|Memory controller support
- Custom controller support—configurable bypass mode that allows you to bypass the hard memory controller and use custom controller.
- Ping Pong controller—allows two instances of the hard memory controller to time-share the same set of address/command pins.
|Interface protocols support
- Supports the Avalon® -MM interface.
- The PHY interface adheres to the AFI protocol.
||You can configure the controller to run at half rate or quarter rate.
|Configurable memory interface width
Supports widths from 8 to 144 bits, in 8-bit increments.
|Multiple rank support
||Supports up to 4 ranks.
||Able to accept bursts of any size up to a maximum burst length of 127 on the local interface of the controller and map the bursts to efficient memory commands.
Note: For applications that must adhere strictly to the Avalon® -MM specification, the maximum burst length is 64.
|Efficiency optimization features
- Open-page policy—by default, data traffic is closed-page on every access. However, the controller keeps a row open based on incoming traffic, which can improve controller efficiency, especially for random traffic.
- Preemptive bank management—the controller can issue bank management commands early, to ensure that the required row is already open when the read or write occurs.
- Data reordering—the controller reorders read and write commands.
- Additive latency—the controller can issue a READ/WRITE command after the ACTIVATE command to the memory bank, before tRCD, which increases the command efficiency
|User requested priority
||You can assign priority to commands. This feature allows you to specify that higher priority commands get issued earlier to reduce latency.
||Ensures all requests are served after a predefined time out period, which ensures that low priority accesses are not left behind while reordering data for efficiency.
|Timing for address/command bus
To maximize command bandwidth, you can double the number of memory commands in one controller clock cycle:
- Quasi-1T addressing for half-rate address/command bus
- Quasi-2T addressing for quarter-rate address/command bus
||Able to issue read or write commands continuously to random addresses. You must correctly cycle the bank addresses.
||The controller controls the on-die termination signal for the memory. This feature improves signal integrity and simplifies your board design.
- User-controlled refresh timing—optionally, you can control when refreshes occur. This allows you to prevent important read or write operations from clashing with the refresh lock-out time.
- Per-rank refresh—allows refresh for each individual rank.
- Controller-controlled refresh.
- 8-bit ECC code; single error correction, double error detection (SECDED).
- User ECC supporting pass-through user ECC bits as part of data bits.
|Power saving features
- Low-power modes (power down and self-refresh)—optionally, you can request that the controller put the memory into one of the two low-power states.
- Automatic power down—puts the memory device in power-down mode when the controller is idle. You can configure the idle waiting time.
- Memory clock gating.
|Mode register set
||Access the memory mode register.
- Bank group support—supports different timing parameters for between bank groups.
- Data Bus CRC—data bus encoding and decoding.
- Command/Address parity—command and address bus parity check.
- Alert reporting—responds to the error alert flag.
- Multipurpose register access—supports multipurpose register access in serial readout mode.
- Fine granularity refresh—supports 1x, 2x, and 4x fixed refresh rates.
- Temperature-controlled refresh—adjusts the refresh rate according to a temperature range.
- Low-power auto self-refresh—operating-temperature-triggered auto adjustment to the self-refresh rate.
- Maximum power savings.
- Deep power-down mode—achieves maximum power reduction by eliminating power to the memory array. Data is not retained when the device enters deep power-down mode.
- Partial array self-refresh.
- Per-bank refresh.
|ZQ calibration command
||Support long or short ZQ calibration command for DDR3 or DDR4.