External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Document Table of Contents

4.4.9. caltiming4

address=35(32 bit)

Field Bit High Bit Low Description Access
cfg_t_param_wr_ap_to_valid 5 0 Write with autoprecharge to valid command timing. Read
cfg_t_param_pch_to_valid 11 6 Precharge to valid command timing. Read
cfg_t_param_pch_all_to_valid 17 12 Precharge all to banks being ready for bank activation command. Read
cfg_t_param_arf_to_valid 25 18 Auto Refresh to valid DRAM command window. Read
cfg_t_param_pdn_to_valid 31 26 Power down to valid bank command window. Read

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