External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023
Public
Document Table of Contents

4.1.4.14. cal_debug_out_reset_n for QDR II/II+/II+ Xtreme

User calibration debug clock domain reset interface

Table 117.  Interface: cal_debug_out_reset_nInterface type: Reset Output
Port Name Direction Description
cal_debug_out_reset_n Output Reset for the user clock connecting to the Avalon calibration debug_out bus. Asynchronous assertion and synchronous deassertion