8.4. QDR II/II+/II+ Xtreme Board Design Guidelines
The following topics focus on the following key factors that affect signal integrity:
- I/O standards
- QDR II SRAM configurations
- Signal terminations
- Printed circuit board (PCB) layout guidelines
QDR II SRAM interface signals use one of the following JEDEC* I/O signaling standards:
- HSTL-15—provides the advantages of lower power and lower emissions.
- HSTL-18—provides increased noise immunity with slightly greater output voltage swings.
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