External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Public
Document Table of Contents

4.1.1.27. ctrl_user_priority for DDR3

Controller user-requested priority interface

Table 35.  Interface: ctrl_user_priorityInterface type: Conduit
Port Name Direction Description
ctrl_user_priority_hi Input When asserted high along with a read or write request to the memory controller, indicates that the request is high priority and should be fullfilled before other low priority requests.

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